A physically unclonable function (PUF) circuit includes a program control transistor, a program select transistor, a read select transistor, and a PUF bit storage transistor. The PUF bit storage transistor has a drain region coupled to the read select transistor, a source region coupled to a source line and the program select transistor, a channel region, a gate dielectric layer, and a gate electrode coupled to the program select transistor. The gate dielectric layer has a first portion formed on the drain region, a second portion formed on the source region, and a main portion formed on the channel region and between the first portion and the second portion, thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer being smaller than a thickness of the main portion of the gate dielectric layer.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The PUF circuit of claim 2, wherein the main gate portion, the first gate extension portion, the second gate extension portion are composed of doped polysilicon, silicide, or metal.
8. The PUF circuit of claim 1 wherein the thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer are substantially equal.
11. The method of claim 9, wherein the high voltage exceeds the gate-to-source/drain breakdown voltage.
12. The method of claim 9, wherein the high voltage is a variable voltage ramping upwards until the gate-to-source/drain breakdown voltage is reached.
13. The method of claim 9, wherein the high voltage ranges from 3V to 10V, the program control voltage ranges from 3V to 10V, and the program select voltage ranges from 1V to 3V, and the read select voltage ranges from 3V to 10V.
14. The method of claim 9, wherein the at least a program control transistor is turned on by the program control voltage, the at least a program select transistor is turned on by the at least a program select voltage, and the at least a read select transistor is turned on by the read select voltage.
16. The method of claim 15, wherein the bit line voltage ranges from 0.5V to 2V, the ground voltage is substantially 0V, and the read select voltage ranges from 1V to 3V.
17. The method of claim 15, wherein the at least a program control transistor and the at least a program select transistor are turned off by the ground voltage, and the at least a read select transistor is turned on by the read select voltage.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 17, 2020
September 6, 2022
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