Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The integrated assembly of claim 1 wherein the first conductive lines are electrically coupled with sense-amplifier-circuitry, and wherein the second conductive lines are electrically coupled with driver circuitry.
3. The integrated assembly of claim 1 wherein the active structures are vertically-extending pillars of semiconductor material.
4. The integrated assembly of claim 1 wherein the second set of the capacitors provides a total capacitance within a range of from about 3 pF to about 30 pF.
5. The integrated assembly of claim 1 wherein the shield structures are a first set of the shield structures, and wherein the voltage source is a first voltage source; and further comprising a second set of the shield structures electrically coupled to a second voltage source through a third set of the capacitors.
7. The integrated assembly of claim 6 wherein the shield structures of the first set alternate with the shield structures of the second set along the second direction.
10. The integrated assembly of claim 9 wherein the conductive structures are aligned with the first conductive lines and are in one-to-one correspondence with the first conductive lines.
11. The integrated assembly of claim 9 wherein the capacitors of the first set are comprised by memory cells of a memory array; and wherein the third conductive line is in a continuous ON state during operation of memory cells of the memory array.
12. The integrated assembly of claim 9 wherein the capacitors of the first set are comprised by memory cells of a memory array; and wherein the third conductive line is not in a continuous ON state during operation of memory cells of the memory array.
14. The integrated assembly of claim 13 wherein the second nodes are part of a continuous conductive expanse that extends across the capacitors of the first and second sets.
15. The integrated assembly of claim 1 wherein the shield structures extend upwardly from a conductive plate, with said conductive plate extending to under the first conductive lines.
17. The integrated assembly of claim 16 wherein the first conductive lines are electrically coupled with sense-amplifier-circuitry, and wherein the second conductive lines are electrically coupled with driver circuitry.
18. The integrated assembly of claim 16 wherein the active structures are vertically-extending pillars of comprising silicon.
19. The integrated assembly of claim 16 wherein the second set of the capacitors provides a total capacitance within a range of from about 3 pF to about 30 pF.
20. The integrated assembly of claim 16 wherein the second set of the capacitors provides a total capacitance within a range of from about 5 pF to about 20 pF.
22. The integrated assembly of claim 21 wherein the conductive structures are aligned with the first conductive lines and are in one-to-one correspondence with the first conductive lines.
23. The integrated assembly of claim 16 wherein the first nodes are configured as upwardly-opening containers, and wherein the second nodes extend into the upwardly-opening containers.
25. The integrated assembly of claim 24 wherein the first and second voltage sources are at the same voltage as one another.
26. The integrated assembly of claim 25 wherein the first and second voltage sources are at ground.
27. The integrated assembly of claim 25 wherein the first and second voltage sources are at VCC/2.
28. The integrated assembly of claim 24 wherein the second memory cells are within a memory array, and wherein the second shield lines are subdivided between at least two sets which are operated independently of one another during operation of the memory array.
30. The integrated assembly of claim 29 wherein the second deck includes a third interconnect structure laterally offset form the second digit lines, and on an opposing side of the second digit lines relative to the second interconnect structure; wherein the second digit lines are spaced from one another by gaps; wherein the second shield lines are within some of the gaps; wherein third shield lines are within others of the gaps; and wherein the third shield lines are electrically coupled to the third interconnect structure.
32. The integrated assembly of claim 31 wherein the second and third gating lines remain in an ON state during operation of the memory array.
33. The integrated assembly of claim 31 wherein the second and third gating lines are at a substantially same voltage as one another for an entire duration of operation of the memory array.
34. The integrated assembly of claim 31 wherein the second and third gating lines are at different voltages relative to one another for at least a portion of a duration of operation of the memory array.
35. The integrated assembly of claim 29 wherein the first and second voltage sources are at the same voltage as one another.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 10, 2020
September 6, 2022
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