A split-gate flash memory cell includes a semiconductor substrate having thereon a select gate oxide layer and a floating gate oxide layer. A floating gate is disposed on the floating gate oxide layer. A football-shaped oxide layer is disposed on the floating gate. The floating gate includes tips under the football-shaped oxide layer. A select gate is disposed on the select gate oxide layer and extended onto the football-shaped oxide layer. An inter-poly oxide layer is between the select gate and the floating gate. The inter-poly oxide layer has a thickness smaller than a thickness of the select gate oxide layer. A source region is formed in the semiconductor substrate and adjacent to the floating gate. A drain region is formed in the semiconductor substrate and adjacent to the select gate.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method for forming a split-gate flash memory cell according to claim 1, wherein the first thickness is less than 100 angstroms.
3. The method for forming a split-gate flash memory cell according to claim 1, wherein the remaining thickness is less than 70 angstroms.
4. The method for forming a split-gate flash memory cell according to claim 1, wherein the second thickness is less than 180 angstroms.
5. The method for forming a split-gate flash memory cell according to claim 1, wherein the third thickness is less than 190 angstroms.
6. The method for forming a split-gate flash memory cell according to claim 1, wherein the fourth thickness is less than 200 angstroms.
8. The method for forming a split-gate flash memory cell according to claim 7, wherein the spacer material layer comprises a silicon nitride layer.
9. The method for forming a split-gate flash memory cell according to claim 1, wherein the hard mask layer comprises a silicon nitride layer.
11. The split-gate flash memory cell according to claim 10, wherein the floating gate oxide layer has a thickness less than 100 angstroms.
12. The split-gate flash memory cell according to claim 10, wherein the select gate oxide layer has a thickness less than 200 angstroms.
13. The split-gate flash memory cell according to claim 10, wherein the semiconductor substrate is a silicon substrate, and wherein the select gate oxide layer and the floating gate oxide layer are silicon oxide layers.
14. The split-gate flash memory cell according to claim 10, wherein the football-shaped oxide layer is a silicon oxide layer, and wherein the inter-gate layer is a silicon oxide layer.
15. The split-gate flash memory cell according to claim 10, wherein the spacer comprises a silicon nitride layer.
16. The split-gate flash memory cell according to claim 10, wherein the select gate and the floating gate comprise polysilicon layers.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 18, 2021
September 6, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.