In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The apparatus of claim 1, the package substrate further comprising a damping tab coupled between the die mount portion and the wire bonding portion.
3. The apparatus of claim 2, wherein a shorting bar couples the damping tab to the wire bonding portion.
4. The apparatus of claim 1, wherein the package substrate is a lead frame.
5. The apparatus of claim 1, wherein a width of the slot is at least 0.100 millimeters.
6. The apparatus of claim 1, further comprising at least a second semiconductor die mounted on the die mount portion.
7. The apparatus of claim 1, wherein the split die pad comprises a first split die pad and further comprising a second split die pad having a second die mount portion and a second wire bonding portion spaced from the second die mount portion by a second slot, and at least a second semiconductor die mounted on the second die mount portion.
8. The apparatus of claim 1, wherein more than one semiconductor die is mounted on the die mount portion and the apparatus forms a semiconductor package that is a multichip module (MCM).
9. The apparatus of claim 1, wherein the apparatus forms a semiconductor package that is one selected from a group consisting essentially of: a small outline integrated circuit (SOIC) package, a dual inline package (DIP), a quad. flat package (QFP), and a quad. flat no lead (QFN) package.
12. The method of claim 10, wherein the slot is at least 0.100 mm wide.
14. The method of claim 10, wherein the package substrate is a lead frame.
15. The method of claim 10, wherein the package is one selected from a group consisting essentially of: a small outline integrated circuit (SOIC) package, a dual inline package (DIP), a quad. flat package (QFP), and a quad. flat no lead (QFN) package.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 26, 2020
September 13, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.