A pixel circuit includes a photodiode and a floating diffusion disposed in a semiconductor substrate. A transfer gate is disposed between the photodiode and the floating diffusion to transfer photogenerated image charge from the photodiode to the floating diffusion. A dual floating diffusion (DFD) transistor is coupled between the floating diffusion and a DFD capacitor. The DFD transistor includes a DFD gate that includes a planar gate portion disposed over a surface of the semiconductor substrate and a vertical gate portion that extends vertically from the planar gate portion into the semiconductor substrate. The vertical gate portion of the DFD gate is configured to increase a gate to substrate coupling capacitance of the DFD transistor. The gate to substrate coupling capacitance and the DFD capacitor are coupled to increase an effective capacitance associated with the floating diffusion in response to the DFD transistor being turned on.
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2. The pixel circuit of claim 1, further comprising a gate oxide disposed between the DFD gate structure and the semiconductor substrate.
3. The pixel circuit of claim 2, wherein the gate oxide has a thickness of approximately 30 to 45 angstroms between the DFD gate structure and the semiconductor substrate.
4. The pixel circuit of claim 1, wherein a conversion gain of the pixel circuit is configured to be decreased in response to the DFD transistor being turned on, wherein the conversion gain of the pixel circuit is configured to be increased in response to the DFD transistor being turned off.
5. The pixel circuit of claim 1, wherein the vertical gate portion is a first vertical gate portion of a plurality of vertical gate portions included in the DFD gate structure, wherein each one of the plurality of vertical gate portions extends vertically from the planar gate portion into the semiconductor substrate between a source region and a drain region of the DFD transistor.
6. The pixel circuit of claim 5, wherein the plurality of vertical gate portions further includes a second vertical gate portion, wherein the first vertical gate portion and the second vertical gate portion are arranged along a channel width direction of the DFD transistor between the drain region and the source region of the DFD transistor to form vertical channels along the first vertical gate portion and the second vertical gate portion between the source region and the drain region of the DFD transistor.
7. The pixel circuit of claim 6, wherein the plurality of vertical gate portions are arranged in an M×N arrangement from the planar gate portion into the semiconductor substrate.
9. The pixel circuit of claim 8, wherein a pillar structure of the vertical gate portion of the transfer gate has a same pillar structure as a pillar structure of the DFD gate structure.
10. The pixel circuit of claim 1, wherein the photodiode is first photodiode of a plurality of photodiodes, wherein each one of the plurality of photodiodes is disposed in the semiconductor substrate and configured to photogenerate image charge in response to incident light.
12. The pixel circuit of claim 1, further comprising a plurality of shallow trench isolation (STI) structures disposed in the semiconductor substrate, wherein each one of the plurality of STI structures includes an oxide material, wherein each one of the plurality of STI structures is arranged in the semiconductor substrate to isolate active regions from transistor regions in the pixel circuit, wherein one of the active regions includes the photodiode and the floating diffusion, and one of the transistor regions includes the DFD transistor.
13. The pixel circuit of claim 12, further comprising a plurality of implanted isolation regions disposed in the semiconductor substrate, wherein the plurality of STI structures are formed in the plurality of implanted isolation regions.
14. The pixel circuit of claim 12, wherein the vertical gate portion of the DFD gate structure extends vertically from the planar gate portion into the semiconductor substrate between a first one of the plurality of STI structures and a second one of the plurality of STI structures.
15. The pixel circuit of claim 14, wherein the vertical gate portion of the DFD gate structure extends vertically from the planar gate portion into the semiconductor substrate to a same depth into the semiconductor substrate as the first one of the plurality of STI structures and the second one of the plurality of STI structures extend vertically into the semiconductor substrate.
17. The imaging system of claim 16, further comprising function logic coupled to the readout circuit to store digital representations of the image charge values from the pixel array.
18. The imaging system of claim 16, wherein each one of the plurality of pixel circuits further comprises a gate oxide disposed between the DFD gate structure and the semiconductor substrate.
19. The imaging system of claim 18, wherein the gate oxide has a thickness of approximately 30 to 45 angstroms between the DFD gate structure and the semiconductor substrate.
20. The imaging system of claim 16, wherein the vertical gate portion is a first vertical gate portion of a plurality of vertical gate portions included in the DFD gate structure, wherein each one of the plurality of vertical gate portions extends vertically from the planar gate portion into the semiconductor substrate between a source region and a drain region of the DFD transistor beneath the surface of the semiconductor substrate.
21. The imaging system of claim 20, wherein the plurality of vertical gate portions further includes a second vertical gate portion, wherein the first vertical gate portion and the second vertical gate portion are arranged along a channel width direction between the drain region and the source region of the DFD transistor to form vertical channels along the first vertical gate portion and the second vertical gate portion between the source region and the drain region of the DFD transistor.
22. The imaging system of claim 21, wherein the plurality of vertical gate portions are arranged in an M×N arrangement from the planar gate portion into the semiconductor substrate.
24. The imaging system of claim 23, wherein a pillar structure of the vertical gate portion of the transfer gate has a same pillar structure as a pillar structure of the DFD gate structure.
25. The imaging system of claim 16, wherein the photodiode is first photodiode of a plurality of photodiodes, wherein each one of the plurality of photodiodes is disposed in the semiconductor substrate and configured to photogenerate image charge in response to incident light.
26. The imaging system of claim 25, wherein the plurality of photodiodes further includes a second photodiode, a third photodiode, and a fourth photodiode arranged symmetrically in the semiconductor substrate around the floating diffusion.
28. The imaging system of claim 16, wherein each one of the plurality of pixel circuits further comprises a plurality of shallow trench isolation (STI) structures disposed in the semiconductor substrate, wherein each one of the plurality of STI structures includes an oxide material, wherein each one of the plurality of STI structures is arranged in the semiconductor substrate to isolate active regions from transistor regions in the pixel circuit, wherein one of active regions includes the photodiode and the floating diffusion, and one of transistor regions includes the DFD transistor.
29. The imaging system of claim 28, wherein the vertical gate portion of the DFD gate structure extends vertically from the planar gate portion into the semiconductor substrate between a first one of the plurality of STI structures and a second one of the plurality of STI structures.
30. The imaging system of claim 28, wherein the vertical gate portion of the DFD gate structure extends vertically from the planar gate portion into the semiconductor substrate to a same depth into the semiconductor substrate as the first one of the plurality of STI structures and the second one of the plurality of STI structures extend vertically into the semiconductor substrate.
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April 13, 2021
September 20, 2022
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