Patentable/Patents/US-11461038
US-11461038

Method, device and terminal for testing memory chip

PublishedOctober 4, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

The present disclosure provides a method, a device and a terminal for testing a memory chip. The method may include setting an attack mode and random attack parameters, generating a random attack command according to the attack mode and random attack parameters, attacking the memory chip according to the random attack command, and testing the attacked memory chip and generating a test result. This method is able to simulate various types of attacks and can thus perform a suitable test on the memory chip for the types of the actual attack. In addition, since the attacks can be randomized to any memory cell of the memory chip, testing of the whole memory chip is made possible.

Patent Claims
8 claims

Legal claims defining the scope of protection, as filed with the USPTO.

3

3. The method of claim 2, wherein setting the attack count includes recording the attack count into the test result when the attack on the memory chip is completed.

6

6. The method of claim 5, wherein the victims of the aggressor comprise adjacent test lines of the aggressor, or test lines spaced apart from the aggressor by at least one test line.

7

7. The method of claim 1, wherein the attack mode comprises Activate, Write, or Read.

13

13. The device of claim 9, wherein the attack count configuration unit is configured to record the attack count into the test result when the attack on the memory chip is completed.

16

16. The terminal of claim 15, wherein setting the attack count includes recording the attack count into the test result when the attack on the memory chip is completed.

17

17. The terminal of claim 14, wherein the aggressor comprises a middle line in the test line set, the test lines comprise word lines, bit lines, or a combination thereof, and the test line set comprises a word line set, or a bit line set, or a combination thereof.

19

19. The terminal of claim 18, wherein the victims of the aggressor comprise adjacent test lines of the aggressor, or test lines spaced apart from the aggressor by at least one test line.

20

20. The terminal of claim 14, wherein the attack mode comprises Activate, Write, or Read.

Classification Codes (CPC)

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Patent Metadata

Filing Date

March 12, 2021

Publication Date

October 4, 2022

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Cite as: Patentable. “Method, device and terminal for testing memory chip” (US-11461038). https://patentable.app/patents/US-11461038

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