Provided is a phase-change memory (PCM) module including a PCM device including a bit line and a word line, a memory controller configured to output a command related to an operation of the PCM device, and an interference mitigation part located between the memory controller and the PCM device and configured to perform a rewrite operation on the basis of a state transition characteristic of the command output from the memory controller.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The phase-change memory module of claim 1, wherein the interference mitigation part calculates a number of 1-to-0 flips of the command and performs a rewrite operation for the command when the calculated number of 1-to-0 flips exceeds a preset threshold value.
5. The phase-change memory module of claim 4, wherein, when the zero flip control variable of one entry included in the main table exceeds the threshold value, the interference mitigation part performs a rewrite operation for the entry.
7. The phase-change memory module of claim 3, wherein the approximate lowest number estimator defines a certain number of main table entries as one group and performs a replacement policy for the main table by applying the defined group as one unit cycle.
8. The phase-change memory module of claim 7, wherein the approximate lowest number estimator sets a random offset for each defined group and performs a read operation on the entries included in the defined group on the basis of the set offset.
9. The phase-change memory module of claim 3, wherein the main table and the buffer table include two sets of static random access memories (SRAMs).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 9, 2021
October 4, 2022
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