Provided is a phase-change memory (PCM) module including a PCM device including a bit line and a word line, a memory controller configured to output a command related to an operation of the PCM device, and an interference mitigation part located between the memory controller and the PCM device and configured to perform a rewrite operation on the basis of a state transition characteristic of the command output from the memory controller.
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2. The phase-change memory module of claim 1, wherein the interference mitigation part calculates a number of 1-to-0 flips of the command and performs a rewrite operation for the command when the calculated number of 1-to-0 flips exceeds a preset threshold value.
Phase-change memory (PCM) is a non-volatile memory technology that stores data by altering the phase of a chalcogenide material between amorphous and crystalline states. A key challenge in PCM is interference, where repeated write operations can degrade adjacent cells due to thermal effects, particularly during 1-to-0 phase transitions (amorphous to crystalline). This degradation reduces data integrity and endurance. The invention addresses this issue with a phase-change memory module that includes an interference mitigation part. This part monitors write operations to detect 1-to-0 flips, which are more disruptive than 0-to-1 flips. The module calculates the number of 1-to-0 flips for a given command and compares it to a preset threshold. If the number exceeds the threshold, the module performs a rewrite operation to mitigate interference. The rewrite operation may involve adjusting the write parameters, such as pulse amplitude or duration, or reallocating data to less affected cells. This dynamic adjustment helps maintain data reliability and extends the memory's lifespan by reducing unintended phase changes in neighboring cells. The threshold can be set based on empirical data or adaptive algorithms to optimize performance.
5. The phase-change memory module of claim 4, wherein, when the zero flip control variable of one entry included in the main table exceeds the threshold value, the interference mitigation part performs a rewrite operation for the entry.
7. The phase-change memory module of claim 3, wherein the approximate lowest number estimator defines a certain number of main table entries as one group and performs a replacement policy for the main table by applying the defined group as one unit cycle.
8. The phase-change memory module of claim 7, wherein the approximate lowest number estimator sets a random offset for each defined group and performs a read operation on the entries included in the defined group on the basis of the set offset.
9. The phase-change memory module of claim 3, wherein the main table and the buffer table include two sets of static random access memories (SRAMs).
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July 9, 2021
October 4, 2022
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