There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The memory device of claim 1, wherein the select transistors are drain select transistors connected to bit lines.
4. The memory device of claim 3, wherein the row decoder sequentially applies the pass voltage and the program voltage to a selected drain select line among the select lines.
5. The memory device of claim 4, wherein the page buffer group applies the program allow voltage to the first bit lines and applies the first program inhibit voltage to the second bit lines, before the pass voltage is applied to the selected drain select line.
6. The memory device of claim 5, wherein the page buffer group applies the program allow voltage and the first program inhibit voltage respectively to the first bit lines and the second bit lines and then controls the first bit lines and the second bit lines to be in a floating state.
7. The memory device of claim 6, wherein the source line driver applies the coupling voltage to the source line from a period in which the first bit lines and the second bit lines are in the floating state.
8. The memory device of claim 7, wherein a potential level of the second bit lines in the floating state is increased to a voltage of a second program inhibit voltage having a potential higher than that of the first program inhibit voltage due to a coupling phenomenon caused by the coupling voltage applied to the source line.
9. The memory device of claim 8, wherein the page buffer group controls a potential of the first bit lines to have a level of the program allow voltage by applying the program allow voltage to the first bit lines in the floating state for a certain time in a period in which the pass voltage is applied to the selected drain select line.
12. The memory device of claim 11, wherein the row decoder sequentially applies the pass voltage and the program voltage to a selected drain select line among the select lines.
13. The memory device of claim 12, wherein the page buffer group applies the program allow voltage to the first bit lines and applies the first program inhibit voltage to the second bit lines for a certain time, before the pass voltage is applied to the selected drain select line, and then controls the first bit lines and the second bit lines to be in a floating state.
14. The memory device of claim 13, wherein the source line driver applies the coupling voltage having a potential higher than that of the first program inhibit voltage to the source line from a period in which the first bit lines and the second bit lines are in the floating state.
15. The memory device of claim 14, wherein the page buffer group controls a potential of the first bit lines to have a level of the program allow voltage by applying the program allow voltage to the first bit lines in the floating state for a certain time in a period in which the pass voltage is applied to the selected drain select line.
17. The method of claim 16, wherein, in the applying of the coupling voltage to the source line, the first bit lines and the second bit lines are controlled to be in a floating state.
18. The method of claim 17, wherein a potential level of the second bit lines in the floating state is increased due to a coupling phenomenon caused by the coupling voltage applied to the source line.
19. The method of claim 18, wherein the coupling voltage has a potential level higher than that of the first program inhibit voltage.
20. The method of claim 16, wherein the program allow voltage is applied to the first bit lines for a certain time in a period in which the pass voltage is applied to the selected drain select line.
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May 7, 2021
October 4, 2022
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