A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein the semiconductor chip has a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure.
3. The method of claim 1, wherein the forming the molding member includes forming the molding member such that a horizontal width of the molding member is greater than a horizontal width of the redistribution line structure, and such that the molding member covers side surfaces of each of the plurality of redistribution line insulating layers.
4. The method of claim 1, wherein the forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers to have a cascade structure.
5. The method of claim 1, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that side surfaces of each of the plurality of redistribution line insulating layers are inclined surfaces each having an acute angle from a normal line with respect to a lower surface of each of the plurality of redistribution line insulating layers.
6. The method of claim 5, wherein an acute angle of a side surface of the redistribution line insulating layer farthest from the semiconductor chip is less than acute angles of side surfaces of the remainder of the plurality of redistribution line insulating layers.
7. The method of claim 1, wherein the forming the molding member includes forming the molding member such that a lower surface of the redistribution line insulating layer farthest from the semiconductor chip is coplanar with a lower surface of the molding member.
8. The method of claim 1, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that a thickness of at least one of the plurality of redistribution line insulating layers is less than thicknesses of the remainder of the plurality of redistribution line insulating layers.
9. The method of claim 8, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that a thickness of the redistribution line insulating layer farthest from the semiconductor chip is less than thicknesses of the remainder of the plurality of redistribution line insulating layers.
10. The method of claim 1, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that at least one of the plurality of redistribution line patterns protrudes, in a horizontal direction, farther outside of a footprint of the semiconductor chip.
12. The method of claim 11, wherein the forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers to have a cascade structure.
13. The method of claim 11, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that side surfaces of each of the plurality of redistribution line insulating layers are inclined surfaces each having an acute angle from a normal line with respect to a lower surface of each of the plurality of redistribution line insulating layers.
14. The method of claim 13, wherein an acute angle of a side surface of the redistribution line insulating layer farthest from the semiconductor chip is less than acute angles of side surfaces of the remainder of the plurality of redistribution line insulating layers.
17. The method of claim 11, wherein the forming of the molding member includes forming the molding member such that the molding member has a horizontal width that is greater than a horizontal width of the redistribution line structure and covers side surfaces of each of the plurality of redistribution line insulating layers.
18. The method of claim 11, wherein the forming the molding member includes forming the molding member such that a lower surface of the redistribution line insulating layer farthest from the semiconductor chip is coplanar with a lower surface of the molding member.
19. The method of claim 11, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that a thickness of the redistribution line insulating layer farthest from the semiconductor chip is less than thicknesses of a remainder of the plurality of redistribution line insulating layers.
20. The method of claim 11, wherein the forming of the redistribution line structure includes forming the redistribution line structure such that at least one of the plurality of redistribution line patterns protrudes, in a horizontal direction, farther outside of a footprint of the semiconductor chip.
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December 3, 2020
October 4, 2022
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