A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
2. The method of claim 1, wherein the semiconductor chip has a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure.
3. The method of claim 1, wherein the forming the molding member includes forming the molding member such that a horizontal width of the molding member is greater than a horizontal width of the redistribution line structure, and such that the molding member covers side surfaces of each of the plurality of redistribution line insulating layers.
4. The method of claim 1, wherein the forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers to have a cascade structure.
5. The method of claim 1, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that side surfaces of each of the plurality of redistribution line insulating layers are inclined surfaces each having an acute angle from a normal line with respect to a lower surface of each of the plurality of redistribution line insulating layers.
6. The method of claim 5, wherein an acute angle of a side surface of the redistribution line insulating layer farthest from the semiconductor chip is less than acute angles of side surfaces of the remainder of the plurality of redistribution line insulating layers.
7. The method of claim 1, wherein the forming the molding member includes forming the molding member such that a lower surface of the redistribution line insulating layer farthest from the semiconductor chip is coplanar with a lower surface of the molding member.
8. The method of claim 1, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that a thickness of at least one of the plurality of redistribution line insulating layers is less than thicknesses of the remainder of the plurality of redistribution line insulating layers.
9. The method of claim 8, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that a thickness of the redistribution line insulating layer farthest from the semiconductor chip is less than thicknesses of the remainder of the plurality of redistribution line insulating layers.
10. The method of claim 1, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that at least one of the plurality of redistribution line patterns protrudes, in a horizontal direction, farther outside of a footprint of the semiconductor chip.
12. The method of claim 11, wherein the forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers to have a cascade structure.
13. The method of claim 11, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that side surfaces of each of the plurality of redistribution line insulating layers are inclined surfaces each having an acute angle from a normal line with respect to a lower surface of each of the plurality of redistribution line insulating layers.
This invention relates to semiconductor packaging, specifically to the formation of redistribution lines (RDLs) with improved insulating layers. The problem addressed is the need for better structural integrity and reliability in RDLs, particularly in preventing delamination or cracking between insulating layers and conductive lines during manufacturing or operation. The method involves forming multiple redistribution line insulating layers with inclined side surfaces. Each insulating layer is deposited such that its side surfaces form an acute angle relative to a normal line perpendicular to the lower surface of the layer. This angled configuration enhances adhesion between adjacent layers and reduces stress concentrations, which are common causes of failure in conventional flat-sided insulating layers. The inclined surfaces also facilitate better filling of gaps during subsequent deposition steps, improving overall structural uniformity. The process may include depositing an insulating material, such as a polymer or dielectric, and then etching or shaping the deposited layer to achieve the desired inclined side profile. The angle of inclination is controlled to balance adhesion strength and manufacturability. This technique is particularly useful in advanced packaging applications where multiple RDL layers are stacked to achieve high-density interconnects. The resulting structure provides improved mechanical stability and electrical performance, extending the lifespan of the semiconductor package.
14. The method of claim 13, wherein an acute angle of a side surface of the redistribution line insulating layer farthest from the semiconductor chip is less than acute angles of side surfaces of the remainder of the plurality of redistribution line insulating layers.
17. The method of claim 11, wherein the forming of the molding member includes forming the molding member such that the molding member has a horizontal width that is greater than a horizontal width of the redistribution line structure and covers side surfaces of each of the plurality of redistribution line insulating layers.
18. The method of claim 11, wherein the forming the molding member includes forming the molding member such that a lower surface of the redistribution line insulating layer farthest from the semiconductor chip is coplanar with a lower surface of the molding member.
19. The method of claim 11, wherein forming of the plurality of redistribution line insulating layers includes forming the plurality of redistribution line insulating layers such that a thickness of the redistribution line insulating layer farthest from the semiconductor chip is less than thicknesses of a remainder of the plurality of redistribution line insulating layers.
This invention relates to semiconductor packaging, specifically to the formation of redistribution lines and insulating layers in a semiconductor device. The problem addressed is optimizing the structural integrity and electrical performance of redistribution layers (RDLs) in semiconductor packages, particularly in multi-layer configurations where varying thicknesses of insulating layers can improve reliability and reduce stress. The method involves forming multiple redistribution line insulating layers over a semiconductor chip, where each layer supports conductive redistribution lines that electrically connect the chip to external components. A key aspect is that the insulating layer farthest from the semiconductor chip is made thinner than the other insulating layers. This design reduces overall package height while maintaining mechanical stability and electrical insulation. The thinner outermost layer minimizes stress concentrations that could otherwise lead to delamination or cracking, especially in high-density interconnect structures. The remaining insulating layers are thicker to provide robust support for the redistribution lines and ensure reliable signal transmission. The technique is particularly useful in advanced packaging applications where space constraints and performance demands are critical.
20. The method of claim 11, wherein the forming of the redistribution line structure includes forming the redistribution line structure such that at least one of the plurality of redistribution line patterns protrudes, in a horizontal direction, farther outside of a footprint of the semiconductor chip.
This invention relates to semiconductor packaging, specifically to methods of forming redistribution line structures that extend beyond the footprint of a semiconductor chip. The problem addressed is the need for improved electrical connectivity and space efficiency in semiconductor devices, particularly where additional routing or connection points are required outside the chip's original boundaries. The method involves forming a redistribution line structure on a semiconductor chip, where the structure includes multiple redistribution line patterns. At least one of these patterns is designed to protrude horizontally beyond the chip's footprint, allowing for extended electrical connections or routing paths. This protrusion enables direct connections to external components or substrates without requiring additional layers or complex routing within the chip's boundaries. The redistribution line structure may be formed using standard semiconductor fabrication techniques, such as photolithography, etching, and metallization, ensuring compatibility with existing manufacturing processes. The protruding pattern can be used for various purposes, including fan-out routing, interconnection with other chips, or integration with package substrates. This approach enhances design flexibility and reduces the need for additional packaging layers, improving overall device performance and reducing manufacturing complexity.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 3, 2020
October 4, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.