A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein the forming the first bridge structure comprises a dual damascene process.
3. The method of claim 2, wherein a dual damascene structure formed by the dual damascene process comprises a via and the conductive trace over and joined with the via, and wherein the via is in physical contact with a through-via in the plurality of through-vias.
4. The method of claim 1, wherein the forming the first bridge structure comprises a single damascene process.
8. The method of claim 1, wherein entireties of the second chip and the third chip overlap the first chip, and the first chip extends laterally beyond all edges of the second chip and the third chip.
10. The method of claim 9 further comprising packaging the package into an additional package.
12. The method of claim 11, wherein the additional bridge structure comprises a first via and a second via connected to through-vias in the second chip and the third chip, respectively.
14. The package of claim 13, wherein the bridge structure further comprises a first via in physical contact with a first through-via of the plurality of through-vias.
15. The package of claim 14, wherein the bridge structure further comprises a second via in physical contact with a second through-via of the plurality of through-vias.
16. The package of claim 13, wherein each of the plurality of through-vias penetrates through the semiconductor substrate.
18. The package of claim 17 comprising a power supplying path, wherein the power supplying path comprises the through-via, a second interconnect structure of the second chip, the bridge structure, and a third interconnect structure of the third chip.
19. The package of claim 17, wherein the first chip comprises a dual damascene structure on the backside of the semiconductor substrate, and wherein the dual damascene structure comprises a via, and the via is in physical contact with the through-via.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 22, 2020
October 4, 2022
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