The present application provides a memory device with air gaps for reducing capacitive coupling. The memory device includes: a substrate, a word line, a bit line, a conductive pillar, a landing pad and a storage capacitor. The substrate has an active region. The word line is formed in the substrate and intersected with the active region. The bit line extends over the substrate and electrically connected to the active region. The conductive pillar is disposed over the substrate and electrically connected to the active region. The conductive pillar and the bit line are located at opposite sides of the word line. The landing pad is disposed on and electrically connected to the conductive pillar. A sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad. The storage capacitor is disposed over and electrically connected to the landing pad.
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2. The memory device according to claim 1, wherein the first and second conductive pillars as well as the first and second landing pads are located at the same side of the word line.
A memory device includes a word line and a memory cell structure formed on one side of the word line. The memory cell structure comprises first and second conductive pillars and first and second landing pads. The first conductive pillar is electrically connected to a first landing pad, and the second conductive pillar is electrically connected to a second landing pad. The first and second conductive pillars and the first and second landing pads are all positioned on the same side of the word line. This configuration allows for a compact and efficient memory cell design, reducing the overall footprint of the memory device. The conductive pillars and landing pads may be used to form memory elements such as resistive memory cells, where the conductive pillars provide electrical pathways to the memory elements, and the landing pads facilitate connections to peripheral circuitry. The arrangement ensures proper alignment and electrical connectivity while minimizing structural complexity. This design is particularly useful in high-density memory arrays where space optimization is critical.
3. The memory device according to claim 1, wherein a space between the first and second landing pads is sealed by the dielectric layer.
4. The memory device according to claim 1, wherein a footprint area of the first landing pad is greater than a footprint area of the first conductive pillar, and a footprint area of the second landing pad is greater than a footprint area of the second conductive pillar.
A memory device includes a first conductive pillar and a second conductive pillar, each electrically connected to a memory cell. The first conductive pillar is coupled to a first landing pad, and the second conductive pillar is coupled to a second landing pad. The footprint area of the first landing pad is larger than the footprint area of the first conductive pillar, and the footprint area of the second landing pad is larger than the footprint area of the second conductive pillar. This design improves electrical connectivity and reliability by providing a larger contact area between the landing pads and the conductive pillars, reducing resistance and enhancing signal integrity. The memory device may be part of a semiconductor structure, such as a three-dimensional memory array, where precise alignment and stable electrical connections are critical. The landing pads serve as intermediate connection points, facilitating manufacturing processes and ensuring robust electrical pathways. The conductive pillars may be vertically aligned within the memory device, with the landing pads positioned at specific levels to optimize space utilization and electrical performance. This configuration helps mitigate misalignment issues during fabrication and improves overall device yield.
5. The memory device according to claim 1, wherein a lateral distance between the first and second landing pads is shorter than a lateral distance between the first and second conductive pillars.
9. The memory device according to claim 8, wherein a footprint area of the first landing pad is greater than a footprint area of the first capacitor plug, and a footprint area of the second landing pad is greater than a footprint area of the second capacitor plug.
12. The memory device according to claim 11, wherein the first contact structure is shorter than the second contact structure.
13. The memory device according to claim 10, wherein a footprint area of the landing pad is greater than a footprint area of the conductive pillar.
14. The memory device according to claim 10, wherein an extending direction of the word line is intersected with an extending direction of the bit line and an extending direction of the active region.
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June 25, 2020
October 11, 2022
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