The present application provides a memory device with air gaps for reducing capacitive coupling. The memory device includes: a substrate, a word line, a bit line, a conductive pillar, a landing pad and a storage capacitor. The substrate has an active region. The word line is formed in the substrate and intersected with the active region. The bit line extends over the substrate and electrically connected to the active region. The conductive pillar is disposed over the substrate and electrically connected to the active region. The conductive pillar and the bit line are located at opposite sides of the word line. The landing pad is disposed on and electrically connected to the conductive pillar. A sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad. The storage capacitor is disposed over and electrically connected to the landing pad.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The memory device according to claim 1, wherein the first and second conductive pillars as well as the first and second landing pads are located at the same side of the word line.
3. The memory device according to claim 1, wherein a space between the first and second landing pads is sealed by the dielectric layer.
4. The memory device according to claim 1, wherein a footprint area of the first landing pad is greater than a footprint area of the first conductive pillar, and a footprint area of the second landing pad is greater than a footprint area of the second conductive pillar.
5. The memory device according to claim 1, wherein a lateral distance between the first and second landing pads is shorter than a lateral distance between the first and second conductive pillars.
9. The memory device according to claim 8, wherein a footprint area of the first landing pad is greater than a footprint area of the first capacitor plug, and a footprint area of the second landing pad is greater than a footprint area of the second capacitor plug.
12. The memory device according to claim 11, wherein the first contact structure is shorter than the second contact structure.
13. The memory device according to claim 10, wherein a footprint area of the landing pad is greater than a footprint area of the conductive pillar.
14. The memory device according to claim 10, wherein an extending direction of the word line is intersected with an extending direction of the bit line and an extending direction of the active region.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 25, 2020
October 11, 2022
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