A semiconductor package may include a package substrate, a molded interposer package (MIP) and a first stiffener. The MIP may be arranged on the package substrate. The MIP may include an interposer, at least one first semiconductor chip and at least one second semiconductor chip molded by a molding member. The first stiffener may be attached to any one of outer surfaces of the MIP. The first stiffener may be spaced apart from the upper surface of the package substrate to suppress a warpage of the MIP. Thus, central conductive bumps between the MIP and the package substrate may not be upwardly floated to improve an electrical connection between the central conductive bumps and the package substrate. Further, a short between edge conductive bumps between the MIP and the package substrate may not be generated.
Legal claims defining the scope of protection, as filed with the USPTO.
6. The semiconductor package of claim 5, wherein each of the first stiffeners has a length in the first direction substantially same as a length of the outer surface of the first molding portions.
7. The semiconductor package of claim 5, wherein the first stiffeners comprises aluminum.
13. The semiconductor package of claim 11, wherein a thickness of the first stiffener is less than or equal to a thickness of the molding member.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 29, 2021
October 11, 2022
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