Provided is a system-on-chip. A central controller is configured to, in response to a request from a host, generate a first signal for requesting error information related to an error from a design of an IP. A local controller is configured to generate a second signal including the error information of the target IP if the request from the host is determined to be for the target IP based on the first signal.
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5. The system-on-chip of claim 4, wherein the local controller is configured to receive the error information of the target semiconductor chip design obtained from the target semiconductor chip design when the identifier of the first signal matches the stored or assigned identifier.
6. The system-on-chip of claim 1, wherein the error information relates to whether the error occurs in the target semiconductor chip design.
7. The system-on-chip of claim 1, wherein the error information relates to a type of the error occurring from the target semiconductor chip design.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 30, 2019
October 11, 2022
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