Semiconductor devices and methods of forming the same are provided. The methods may include forming a stacked structure that may include a stacking area and a stepped area and may include first layers and second layers alternately stacked. The second layers may have a stepped shape in the stepped area, and the stepped area may include at least one flat area and at least one inclined stepped area. The methods may also include forming a capping insulating layer covering the stacked structure. The capping insulating layer may include a first capping region having a first upper surface and a second capping region having a second upper surface at a lower level than the first upper surface. The methods may further include patterning the capping insulating layer to form protrusions at least one of which overlaps the stepped area and then planarizing the capping insulating layer.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, further comprising, after forming the partially etched capping insulating layer, prior to the annealing process, removing the planarization stop layer to expose the uppermost layer of the stacked structure.
3. The method of claim 1, wherein the stepped area of the stacked structure comprises at least one flat area and at least one inclined stepped area adjacent to the at least one flat area.
4. The method of claim 3, wherein one of the plurality of protrusions overlaps the at least one inclined step area.
5. The method of claim 1, wherein at least a portion of each of the plurality of protrusions is removed during planarizing the capping insulating layer.
7. The method of claim 6, wherein the first height is less than a thickness of each of the plurality of second layers.
9. The method of claim 1, wherein the partially etched capping insulating layer includes an upper surface at a level between a lower surface of the planarization stop layer and an upper surface of the planarization stop layer.
10. The method of claim 1, wherein a volume of the partially etched capping insulating layer is reduced by performing the annealing process.
11. The method of claim 1, wherein the annealing process is performed for 30 minutes to 2 hours at a temperature of 500° C. to 850° C.
12. The method of claim 1, wherein patterning the capping insulating layer includes sequentially performing a plurality of etching processes on the capping insulating layer, and each of the plurality of protrusions is formed by performing a respective one of the plurality of etching processes.
15. The method of claim 14, further comprising, after planarizing the first capping insulating layer, performing a first annealing process to increase a density of the first capping insulating layer by reducing a volume of the first capping insulating layer.
17. The method of claim 16, further comprising, after planarizing the second capping insulating layer, performing a second annealing process to increase a density of the second capping insulating layer by reducing a volume of the second capping insulating layer.
18. The method of claim 16, further comprising forming a vertical memory structure extending through the second stacked structure and the first stacked structure after planarizing the second capping insulating layer.
20. The method of claim 19, wherein at least one of the plurality of protrusions comprises opposing sides that have different inclinations, and a first side of the opposing sides that is closer to the stacking area is steeper than a second side opposite to the first side.
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September 29, 2020
October 25, 2022
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