An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The integrated circuit according to claim 1, wherein the first area comprises a dense area, the second area comprises an isolated area, and the dense area is right next to the isolated area.
3. The integrated circuit according to claim 1, wherein the first slot pattern has a minimum size larger than a minimum size of the line patterns.
4. The integrated circuit according to claim 1, wherein the line patterns comprise gate patterns, fin patterns, spacer patterns or mask patterns.
5. The integrated circuit according to claim 1, wherein the rectangular protruding part has a minimum size larger than a minimum size of the line pattern, and the minimum size is with respect to a width of a line of the line patterns and a width of the rectangular protruding part, respectively.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 16, 2018
October 25, 2022
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