A clock sweeping system includes multiple delay elements and a selection circuit. The delay elements are configured to generate multiple delayed clock signals. Each delay element is configured to receive an input signal and delay the input signal to generate a corresponding first delayed clock signal. The input signal is one of a first clock signal, a second clock signal, and a corresponding output signal generated by a previous delay element. The selection circuit is configured to select and output, based on a first select signal for a plurality of times, a corresponding second delayed clock signal as a first output clock signal. The selection circuit is further configured to select and output, based on a second select signal, one of the first and second clock signals as a second output clock signal. The first output clock signal is asynchronous with respect to the second output clock signal.
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3. The clock sweeping system of claim 2, further comprising a third multiplexer that is coupled with the plurality of delay elements, and configured to receive the second select signal and the first and second clock signals, and select and provide, based on the second select signal, one of the first and second clock signals to the plurality of delay elements, wherein when the third multiplexer selects the first clock signal, the second multiplexer selects the second clock signal, and when the third multiplexer selects the second clock signal, the second multiplexer selects the first clock signal.
4. The clock sweeping system of claim 3, further comprising a mode selector that is coupled with the first through third multiplexers, and configured to receive first through third control signals, generate the first and second select signals based on one of the first through third control signals, and provide the first select signal to the first multiplexer and the second select signal to the second and third multiplexers.
This invention relates to clock sweeping systems used in integrated circuits, particularly for testing and debugging purposes. The system addresses the challenge of efficiently routing and selecting clock signals in a circuit to identify timing-related issues or verify functionality. The system includes multiple multiplexers that route clock signals to different components or test points within the circuit. A mode selector is coupled to these multiplexers and receives control signals to dynamically configure the routing paths. The mode selector generates select signals that determine which clock signal is passed through each multiplexer. The first select signal controls the first multiplexer, while the second select signal controls both the second and third multiplexers. This configuration allows flexible switching between different clock sources or test modes, enabling comprehensive testing and analysis of the circuit's timing behavior. The system ensures precise control over clock signal distribution, facilitating accurate diagnosis of timing faults and validation of circuit performance under various conditions.
7. The clock sweeping system of claim 4, further comprising a second control circuit that is coupled with the mode selector, and configured to receive the first and second clock signals, and generate the third control signal.
A clock sweeping system is designed to dynamically adjust clock signals in electronic circuits to optimize performance and power efficiency. The system addresses the challenge of maintaining stable and efficient clock distribution in integrated circuits, particularly in scenarios where varying operational conditions require adaptive clock management. The system includes a mode selector that determines the operational mode of the circuit, such as active, standby, or low-power modes, and generates a first control signal based on the selected mode. A first control circuit receives first and second clock signals and generates a second control signal to adjust the clock distribution network accordingly. The system further includes a second control circuit coupled with the mode selector, which also receives the first and second clock signals and generates a third control signal. This third control signal further refines the clock distribution, ensuring precise timing adjustments based on the operational mode and current clock conditions. The combined control signals enable the system to dynamically switch between different clock configurations, optimizing power consumption and performance across various operating conditions. The system is particularly useful in modern integrated circuits where energy efficiency and performance scalability are critical.
10. The SoC of claim 8, further comprising first and second register sets that are coupled with the first and second multiplexers, and configured to generate and provide the first and second select signals to the first and second multiplexers, respectively.
11. The SoC of claim 8, wherein the clock sweeping system further comprises a third multiplexer that is coupled with the first and second multiplexers and the plurality of delay elements, and configured to receive the fourth select signal and the first and second clock signals, and select and provide one of the first and second clock signals based on the fourth select signal to the plurality of delay elements.
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December 31, 2020
October 25, 2022
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