A clock sweeping system includes multiple delay elements and a selection circuit. The delay elements are configured to generate multiple delayed clock signals. Each delay element is configured to receive an input signal and delay the input signal to generate a corresponding first delayed clock signal. The input signal is one of a first clock signal, a second clock signal, and a corresponding output signal generated by a previous delay element. The selection circuit is configured to select and output, based on a first select signal for a plurality of times, a corresponding second delayed clock signal as a first output clock signal. The selection circuit is further configured to select and output, based on a second select signal, one of the first and second clock signals as a second output clock signal. The first output clock signal is asynchronous with respect to the second output clock signal.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The clock sweeping system of claim 2, further comprising a third multiplexer that is coupled with the plurality of delay elements, and configured to receive the second select signal and the first and second clock signals, and select and provide, based on the second select signal, one of the first and second clock signals to the plurality of delay elements, wherein when the third multiplexer selects the first clock signal, the second multiplexer selects the second clock signal, and when the third multiplexer selects the second clock signal, the second multiplexer selects the first clock signal.
4. The clock sweeping system of claim 3, further comprising a mode selector that is coupled with the first through third multiplexers, and configured to receive first through third control signals, generate the first and second select signals based on one of the first through third control signals, and provide the first select signal to the first multiplexer and the second select signal to the second and third multiplexers.
7. The clock sweeping system of claim 4, further comprising a second control circuit that is coupled with the mode selector, and configured to receive the first and second clock signals, and generate the third control signal.
10. The SoC of claim 8, further comprising first and second register sets that are coupled with the first and second multiplexers, and configured to generate and provide the first and second select signals to the first and second multiplexers, respectively.
11. The SoC of claim 8, wherein the clock sweeping system further comprises a third multiplexer that is coupled with the first and second multiplexers and the plurality of delay elements, and configured to receive the fourth select signal and the first and second clock signals, and select and provide one of the first and second clock signals based on the fourth select signal to the plurality of delay elements.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 31, 2020
October 25, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.