Packets to be transmitted from a network device are buffered in queues in a first packet memory. In response to detecting congestion in a queue in the first packet memory, groups of multiple packets are transferred from the first packet memory to a second packet memory, the second packet memory configured to buffer a portion of traffic bandwidth supported by the network device. Prior to transmission of the packets among the one or more groups of multiple packets from the network device, packets among the one or more groups of multiple packets are transferred from the second packet memory back to the first packet memory. The packets transferred from the second packet memory back to the first packet memory are retrieved from the first packet memory and are forwarded to one or more network ports for transmission of the packets from the network device.
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3. The method of claim 2, wherein transferring the one or more groups of multiple packets from the particular egress queue to the second packet memory comprises transferring the one or more groups of multiple packets from a middle portion of the particular egress queue while at least a head portion of the particular egress queue remains in the first packet memory.
This invention relates to packet processing in network systems, specifically improving efficiency in transferring packets from egress queues to memory. The problem addressed is the inefficiency in conventional systems where packets are transferred sequentially from the head of an egress queue, leading to delays and resource contention. The invention describes a method for transferring groups of multiple packets from a particular egress queue to a second packet memory. Unlike traditional approaches, this method transfers packets from a middle portion of the egress queue while the head portion remains in the first packet memory. This allows for parallel processing, reducing latency and improving throughput. The method involves identifying one or more groups of packets within the middle portion of the egress queue and transferring these groups to the second packet memory without disrupting the head portion, which continues to be processed or transmitted. This selective transfer from the middle portion enables more efficient memory management and reduces the likelihood of bottlenecks in packet transmission. The technique is particularly useful in high-speed networking environments where minimizing latency and maximizing throughput are critical.
4. The method of claim 3, further comprising, while the one or more groups of multiple packets from the middle of the particular egress queue are stored in the second packet memory, enqueuing one or more additional packets at a tail of a tail portion of the particular egress queue stored in the first packet memory.
This invention relates to packet processing in network systems, specifically addressing the challenge of efficiently managing packet queues to improve throughput and reduce latency. The method involves dynamically reordering packets within an egress queue to optimize memory usage and processing efficiency. A particular egress queue is divided into segments, with a middle portion of packets temporarily stored in a second packet memory while the remaining packets are retained in a first packet memory. This allows the system to process the middle packets without disrupting the overall queue structure. During this operation, additional packets can be enqueued at the tail of the egress queue in the first packet memory, ensuring continuous packet flow and minimizing delays. The method ensures that packet ordering is preserved while enabling efficient memory management and processing. This approach is particularly useful in high-speed networking environments where minimizing latency and maximizing throughput are critical. The invention improves upon traditional queue management techniques by dynamically adjusting memory allocation and processing order to handle varying network loads and packet sizes efficiently.
6. The method of claim 3, wherein requesting transfer of the packets among the one or more groups of multiple packets comprises requesting transfer of the packets from the middle portion of the particular egress queue from the second packet memory to the first packet in response to detecting that a length of the header portion of the particular egress queue stored in the first packet memory is below a threshold.
7. The method of claim 3, further comprising linking the packets transferred from the second packet memory back to the first packet memory with a tail of the header portion of the particular egress queue in the first packet memory.
In the field of network packet processing, this invention addresses the challenge of efficiently managing packet transfers between memory buffers to optimize data flow in network devices. The method involves transferring packets from a second packet memory to a first packet memory, where the first packet memory contains multiple egress queues for organizing outgoing data. The transferred packets are linked to a specific egress queue in the first packet memory by appending them to the tail of the header portion of that queue. This linking process ensures that the packets are properly integrated into the queue structure, maintaining the correct order and organization of data for subsequent transmission. The method also includes managing the header portion of the egress queue, which may involve updating pointers or metadata to reflect the addition of new packets. By efficiently linking packets to the appropriate egress queue, the invention improves the performance and reliability of packet processing in network devices, particularly in high-speed or high-volume data environments. The technique is particularly useful in scenarios where packets must be dynamically routed or reordered based on network conditions or priority settings.
14. The network device of claim 13, wherein the packet processor is configured to transfer the one or more groups of multiple packets from a middle portion of the particular egress queue while at least a head portion of the particular egress queue remains in the first packet memory.
Network devices manage packet transmission by organizing data into egress queues for efficient processing. A common challenge is optimizing packet transfer to avoid bottlenecks, particularly when handling large or variable-sized data groups. Existing solutions often rely on sequential processing, which can lead to inefficiencies when transferring packets from the head of the queue, especially in high-traffic scenarios. This invention addresses the problem by introducing a network device with a packet processor that selectively transfers groups of multiple packets from the middle portion of an egress queue while retaining the head portion in the first packet memory. This approach allows for more flexible and efficient packet management, reducing latency and improving throughput. The packet processor dynamically identifies optimal transfer points within the queue, ensuring that critical or time-sensitive packets at the head are prioritized while less urgent packets are moved from intermediate positions. The system also includes mechanisms to track packet order and integrity, ensuring seamless transmission without data loss or corruption. By decoupling the transfer of middle-portion packets from the head, the device enhances overall network performance, particularly in environments with bursty or unpredictable traffic patterns. The invention is applicable to routers, switches, and other networking hardware where efficient packet handling is critical.
15. The network device of claim 14, wherein the packet processor is further configured to, while the one or more groups of multiple packets from the middle of the particular egress queue are stored in the second packet memory, enqueue one or more additional packets at a tail of a tail portion of the particular egress queue stored in the first packet memory.
This invention relates to network devices and methods for managing packet processing in high-speed networking systems. The problem addressed is the efficient handling of packet queues to prevent congestion and improve throughput, particularly when processing groups of packets from the middle of an egress queue. The network device includes a packet processor and at least two packet memories. The packet processor is configured to transfer one or more groups of multiple packets from the middle of a particular egress queue stored in a first packet memory to a second packet memory for processing. While these middle packets are being processed in the second memory, the packet processor continues to enqueue additional packets at the tail of the same egress queue in the first memory. This allows the device to maintain continuous packet flow without stalling, even when processing packets from non-sequential positions in the queue. The system ensures that the tail portion of the egress queue remains available for new packet additions while the middle packets are being processed elsewhere, optimizing memory usage and reducing latency. The invention is particularly useful in high-performance networking environments where real-time packet processing is critical.
17. The network device of claim 14, wherein the packet processor is configured to request transfer of packets among the one or more groups of multiple packets from the middle portion of the particular egress queue from the second packet memory to the first packet in response to detecting that a length of the header portion of the particular egress queue stored in the first packet memory is below a threshold.
This invention relates to network devices and methods for managing packet processing in high-speed data networks. The problem addressed is inefficient packet transfer and memory utilization in network devices, particularly when handling large volumes of data with varying packet sizes. The solution involves a network device with a packet processor that dynamically adjusts packet transfer operations based on the state of egress queues. The network device includes multiple packet memories and a packet processor that organizes packets into groups. The packet processor monitors the length of the header portion of an egress queue stored in a first packet memory. When the header portion falls below a predefined threshold, the packet processor initiates a transfer of packets from the middle portion of the egress queue. These packets are moved from a second packet memory to the first packet memory, ensuring efficient use of memory resources and maintaining optimal processing performance. This dynamic adjustment prevents bottlenecks and improves overall network throughput by balancing the distribution of packets across memory locations. The system is particularly useful in high-traffic scenarios where packet sizes and arrival rates vary significantly.
18. The network device of claim 14, wherein the packet processor is further configured to link the packets transferred from the second packet memory back to the first packet memory with a tail of the header portion of the particular egress queue in the first packet memory.
This invention relates to network devices that manage packet processing and memory allocation for efficient data transfer. The problem addressed is optimizing packet handling in network devices to reduce latency and improve throughput, particularly when transferring packets between different memory locations. The network device includes a packet processor and at least two packet memories: a first packet memory and a second packet memory. The packet processor is configured to transfer packets from the first packet memory to the second packet memory for processing. After processing, the packets are transferred back to the first packet memory. The packet processor is further configured to link the returned packets to a specific egress queue in the first packet memory by attaching them to the tail of the header portion of that queue. This linking ensures that the processed packets are correctly positioned in the egress queue for subsequent transmission, maintaining proper packet order and minimizing delays. The system may also include a memory controller to manage data transfers between the packet memories and the packet processor, ensuring efficient memory utilization and reducing bottlenecks. The invention improves network performance by streamlining packet movement and reducing the overhead associated with memory management.
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March 18, 2021
October 25, 2022
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