Patentable/Patents/US-11495300
US-11495300

Method and apparatus for PUF generator characterization

PublishedNovember 8, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a testing method for physical unclonable function (PUF) generator includes: verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array; determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the preconfigured logical states; when the first number of first bit cells is less than a first predetermined number, generating a first map under a first set of operation conditions using the PUF generator and a masking circuit, generating a second map under a second set of operation conditions using the PUF generator and the masking circuit, determining a second number of second bit cells, wherein the second bit cells are stable in the first map and unstable in the second map; when the second number of second bit cells is determined to be zero, determining a third number of third bit cells, wherein the third bit cells are stable in the first map and stable in the second map; and when the third number of third bit cells are greater than a second preconfigured number, the PUF generator is determined as a qualified PUF generator.

Patent Claims
5 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 2

Original Legal Text

2. The method of claim 1, wherein the first set of operation conditions comprises stressed operation conditions, wherein the stressed operation conditions are configured by a controller.

Plain English translation pending...
Claim 3

Original Legal Text

3. The method of claim 2, wherein the controller comprises a delay circuit configured to tune relative timing between signals to provide the stressed operation conditions.

Plain English Translation

This invention relates to semiconductor testing, specifically methods for evaluating integrated circuits under stressed operating conditions to identify potential failures. The method involves applying controlled stress conditions to a semiconductor device to test its reliability and performance under extreme or non-standard operating environments. A controller is used to manage the testing process, including the application of stress conditions and the monitoring of device behavior. The controller includes a delay circuit that adjusts the timing between signals to create the desired stressed conditions. By precisely tuning the timing relationships between signals, the delay circuit ensures that the semiconductor device experiences the intended stress levels, such as voltage, temperature, or signal timing variations, which may reveal latent defects or weaknesses in the device. The method allows for systematic evaluation of device reliability under various stress scenarios, helping manufacturers identify and address potential failure points before deployment. The delay circuit's ability to fine-tune signal timing ensures accurate and repeatable stress testing, improving the reliability of the testing process. This approach is particularly useful in quality assurance and failure analysis for semiconductor devices, ensuring they meet performance and durability standards.

Claim 4

Original Legal Text

4. The method of claim 1, wherein the second set of operation conditions comprises different temperatures and operational voltage levels configured by the controller.

Plain English Translation

This invention relates to a method for optimizing the operation of a system by dynamically adjusting operational conditions based on performance metrics. The system includes a controller that monitors performance data and adjusts operational parameters to improve efficiency, reliability, or other performance factors. The method involves configuring a first set of operation conditions, such as temperature and voltage levels, and then transitioning to a second set of operation conditions that differ from the first set. The second set includes different temperatures and operational voltage levels, which are selected and applied by the controller to achieve desired performance outcomes. The controller may use feedback from sensors or other monitoring systems to determine when and how to adjust these conditions. This approach allows the system to adapt to varying operational demands, environmental factors, or degradation over time, ensuring optimal performance under different scenarios. The method is particularly useful in systems where maintaining stable operation under fluctuating conditions is critical, such as in power management, industrial processes, or electronic devices. By dynamically adjusting temperature and voltage, the system can balance efficiency, longevity, and reliability.

Claim 9

Original Legal Text

9. The PUF generator of claim 8, wherein the first set of operation conditions comprises stressed operation conditions and the second set of operation conditions comprises different temperatures and operational voltage levels.

Plain English translation pending...
Claim 20

Original Legal Text

20. The PUF generator of claim 15, wherein the first set of operation conditions comprises stressed operation conditions and the second set of operation conditions comprises different temperatures and operational voltage levels.

Plain English Translation

A PUF (Physically Unclonable Function) generator is used in hardware security to produce unique, unpredictable digital outputs based on intrinsic physical variations in semiconductor manufacturing. The challenge is ensuring reliability and uniqueness under varying environmental and operational conditions. This invention improves PUF reliability by using a two-step process. First, the PUF is evaluated under stressed conditions, such as extreme voltage or temperature, to identify stable and unstable response bits. Second, the PUF is tested under different temperatures and operational voltage levels to further refine the selection of stable bits. The generator includes a control module that applies these conditions, a measurement module to capture PUF responses, and a selection module to filter out unstable bits. The result is a more reliable PUF output that remains consistent despite environmental variations, enhancing security applications like device authentication and key generation. The invention addresses the problem of PUF instability by systematically evaluating and selecting bits that exhibit consistent behavior across diverse operating conditions.

Classification Codes (CPC)

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Patent Metadata

Filing Date

September 8, 2020

Publication Date

November 8, 2022

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