Patentable/Patents/US-11495317
US-11495317

Managed-NAND real time analyzer and method

PublishedNovember 8, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.

Patent Claims
8 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 4

Original Legal Text

4. The testing device of claim 3, including processing circuitry and a display, wherein the processing circuitry is configured to display a distribution of types of memory operations performed in a physical address space.

Plain English translation pending...
Claim 9

Original Legal Text

9. The testing device of claim 8, wherein the electronic system is a mobile phone system.

Plain English translation pending...
Claim 12

Original Legal Text

12. The method of claim 11, wherein the logging memory events includes logging a physical memory address accessed in association with a detected memory operation.

Plain English translation pending...
Claim 13

Original Legal Text

13. The method of claim 12, including displaying a distribution of types of memory operations performed in a physical address space.

Plain English translation pending...
Claim 17

Original Legal Text

17. The method of claim 10, wherein operating a M-NAND memory device under test includes operating a universal flash storage (UFS) device embedded in an electronic system to receive memory access requests from the electronic system and to provide one or both of status and data to the electronic system at the same rate it receives memory access requests.

Plain English translation pending...
Claim 18

Original Legal Text

18. The method of claim 10, wherein operating a M-NAND memory device under test includes operating a universal flash storage (UFS) device or an embedded MultiMediaCard (eMMC) in a mobile phone system.

Plain English translation pending...
Claim 21

Original Legal Text

21. The non-transitory computer readable storage medium of claim 20, further including instructions configured to cause the processing circuitry of the testing device to display a distribution of types of memory operations according to physical address space.

Plain English translation pending...
Claim 25

Original Legal Text

25. The non-transitory computer readable storage medium of claim 19, further including instructions configured to cause the processing circuitry of the M-NAND testing device to operate a universal flash storage (UFS) device embedded in a mobile phone system as the M-NAND memory device under test.

Plain English translation pending...
Classification Codes (CPC)

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Patent Metadata

Filing Date

June 26, 2019

Publication Date

November 8, 2022

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