A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.
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2. The system of claim 1, wherein the storage controller is to first send a command signal to the NVM devices, and next send a control signal to the data buffer, wherein the control signal is to trigger the data buffer to transfer data to the NVM devices.
3. The system of claim 1, wherein the NVM devices are to operate in a burst mode, to transfer data over 2N cycles, and the data buffer is to operate to transfer data over N cycles, wherein the storage controller is to issue consecutive commands to the data buffer to cause the data buffer to operate for 2N cycles in response to the consecutive commands.
4. The system of claim 3, wherein the data buffer is to eliminate stall cycles internally to produce 2N cycles of continuous data transfer is response to the consecutive commands.
5. The system of claim 1, wherein the data buffer is to apply a first configuration setting to align a data signal on data signal lines of the host-side data bus interface with a strobe signal of the host-side data bus interface and a second configuration setting to align a data signal on data signal lines of the memory-side data bus interface with a strobe signal of the memory-side data bus interface.
6. The system of claim 1, wherein the data buffer is to re-drive data signals from the storage controller to the NVM devices, including to synchronize data to a protocol timing of an interface of the NVM devices.
7. The system of claim 1, wherein the data buffer is to re-drive data signals from the NVM devices to the storage controller, including to synchronize data to a protocol timing of a storage controller interface.
8. The system of claim 1, wherein the NVM devices comprises a first group of NVM devices and the data buffer comprises a first data buffer, and further comprising a second group of NVM devices and a second data buffer coupled between the second group of NVM devices and the storage controller.
The invention relates to a storage system architecture involving non-volatile memory (NVM) devices and data buffers. The system addresses the challenge of efficiently managing data transfer between NVM devices and a storage controller, particularly in scenarios requiring high performance and reliability. The system includes multiple NVM devices organized into distinct groups, such as a first group and a second group. Each group of NVM devices is coupled to a dedicated data buffer, such as a first data buffer for the first group and a second data buffer for the second group. These data buffers act as intermediaries between the NVM devices and the storage controller, facilitating data transfer operations. The storage controller manages the overall operation of the system, including read and write operations to the NVM devices. The use of separate data buffers for different groups of NVM devices allows for parallel data processing, improving system throughput and reducing latency. This architecture also enhances fault isolation, as issues in one group of NVM devices or its associated buffer do not necessarily affect other groups. The system may be implemented in various storage applications, including solid-state drives (SSDs) and other high-performance storage solutions. The design ensures efficient data handling while maintaining reliability and scalability.
9. The system of claim 8, further comprising a third data buffer, wherein the first and second groups of NVM devices couple to the storage controller in a cascaded manner, with the third data buffer coupled between the storage controller and the first and second data buffers.
10. The system of claim 1, further comprising a command buffer coupled between the NVM devices and the storage controller on a command bus, the command buffer to re-drive command signals on the command bus, and synchronize command signals to a clock signal.
12. The system of claim 1, wherein the nonvolatile media comprises a NAND flash memory.
14. The DIMM of claim 13, wherein the storage controller is to first send a command signal to the plurality of NVM devices, and next send a control signal to the data buffer, wherein the control signal is to trigger the data buffer to transfer data to the plurality of NVM devices.
15. The DIMM of claim 13, wherein the data buffer is to re-drive data signals from the storage controller to the plurality of NVM devices, including to synchronize data to a protocol timing of an interface of the plurality of NVM devices.
This invention relates to a dual in-line memory module (DIMM) designed for interfacing with non-volatile memory (NVM) devices, such as solid-state drives (SSDs). The DIMM includes a data buffer that acts as an intermediary between a storage controller and multiple NVM devices. The data buffer is configured to re-drive data signals from the storage controller to the NVM devices, ensuring reliable signal transmission. Additionally, the data buffer synchronizes the data signals to the protocol timing of the NVM device interfaces, aligning the data transfer with the specific timing requirements of the connected NVM devices. This synchronization ensures proper communication and data integrity between the storage controller and the NVM devices. The DIMM may also include a command buffer for managing command signals between the storage controller and the NVM devices, further optimizing data transfer efficiency. The invention addresses the challenge of maintaining high-speed, synchronized data communication in storage systems where multiple NVM devices are connected to a single controller, improving overall system performance and reliability.
16. The DIMM of claim 13, wherein the data buffer is to re-drive data signals from the plurality of NVM devices to the storage controller, including to synchronize data to a protocol timing of a storage controller interface.
17. The DIMM of claim 13, wherein the multiple storage circuits are organized in a cascade, wherein first and second data buffers coupled, respectively, to first and second pluralities of the plurality of NVM devices, and a third data buffer coupled between the first and second data buffers and the storage controller.
19. The DIMM of claim 13, wherein the data buffer is to apply a first configuration setting to align a data signal on data signal lines of the host-side data bus interface with a strobe signal of the host-side data bus interface and a second configuration setting to align a data signal on data signal lines of the memory-side data bus interface with a strobe signal of the memory-side data bus interface.
20. The DIMM of claim 13, wherein the nonvolatile media comprises a NAND flash memory.
A dual in-line memory module (DIMM) integrates nonvolatile memory to enhance data retention during power loss. The module includes a controller and nonvolatile media, such as NAND flash memory, to store data from volatile memory when power is interrupted. The controller manages data transfer between the volatile and nonvolatile memory, ensuring critical data is preserved. The NAND flash memory provides high-density storage, enabling efficient backup of large datasets. This design addresses the vulnerability of traditional DIMMs, which lose data when power is lost, by incorporating persistent storage. The system automatically detects power loss, triggers data transfer, and restores data when power is restored, minimizing data loss. The NAND flash memory's fast write speeds and reliability make it suitable for this application. This solution is particularly useful in servers, data centers, and other systems where data integrity is critical. The module can be integrated into existing systems without significant hardware modifications, offering a cost-effective way to enhance data resilience.
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October 25, 2019
November 15, 2022
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