The present disclosure relates to a method and an apparatus for map reduce. In some embodiments, an exemplary processing unit includes: a 2-dimensional (2D) processing element (PE) array comprising a plurality of PEs, each PE comprising a first input and a second input, the first inputs of the PEs in a linear array in a first dimension of the PE array being connected in series and the second inputs of the PEs in a linear array in a second dimension of the PE array being connected in parallel, each PE being configured to perform an operation on data from the first input or second input; and a plurality of reduce tree units, each reduce tree unit being coupled with the PEs in a linear array in the first dimension or the second dimension of the PE array and configured to perform a first reduction operation.
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4. The processing unit of claim 3, wherein the second reduction operation comprises at least one of addition (ADD) operation, MIN operation, MAX operation, configurable output depth operation, or find operation.
This invention relates to a processing unit designed for efficient data reduction operations in computing systems. The problem addressed is the need for flexible and configurable reduction operations that can handle various types of data processing tasks, such as aggregation, comparison, and selection, while optimizing performance and resource usage. The processing unit includes a first reduction operation that processes input data to generate intermediate results. A second reduction operation is then applied to these intermediate results, where the second operation can be configured to perform different types of reductions. Specifically, the second reduction operation may include addition (ADD), minimum (MIN), maximum (MAX), configurable output depth, or find operations. The configurable output depth allows the processing unit to adjust the number of output values based on the application requirements, while the find operation enables the identification of specific data elements within the processed data. The processing unit is designed to enhance computational efficiency by supporting multiple reduction operations in a single hardware unit, reducing the need for separate specialized components. This flexibility allows the unit to be adapted to various workloads, such as data analytics, machine learning, and real-time processing, where different reduction operations are required. The invention improves performance by minimizing data movement and leveraging parallel processing capabilities, making it suitable for high-performance computing environments.
9. The processing unit of claim 1, wherein the PE is configured to perform at least one of multiplication (MUL) operation, addition (ADD) operation, subtraction (SUB) operation, sum of absolute difference (SAD) operation, absolute value (ABS) operation, shift operation, logical operation, or move (MOV) operation.
17. The method of claim 14, wherein a flex-reduce tree unit or an accumulator of the processing unit is configured to perform a second reduction operation on results of the first reduction operations.
18. The method of claim 14, wherein the plurality of PEs broadcast the second input data into the second linear array of PEs in the second dimension of the 2D PE, the second dimension being different from the first dimension.
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June 12, 2020
November 15, 2022
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