A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.
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2. The method of claim 1, wherein the second dielectric layer is deposited on, and physically contacting, the first dielectric layer, wherein the second dielectric layer is a mono layer, and wherein the implanting the second dielectric layer is performed on the mono layer.
This invention relates to semiconductor fabrication, specifically to methods of forming dielectric layers with implanted regions. The problem addressed is improving the performance and reliability of dielectric layers in semiconductor devices by precisely controlling their properties through implantation techniques. The method involves depositing a second dielectric layer directly on and in physical contact with a first dielectric layer. The second dielectric layer is a monolayer, meaning it is a single atomic or molecular layer thick. After deposition, the second dielectric layer undergoes an implantation process to modify its properties. The implantation is performed directly on the monolayer, allowing for precise control over the doping or defect introduction in the dielectric material. This approach enhances the dielectric's electrical characteristics, such as dielectric constant, leakage current, or breakdown voltage, which are critical for semiconductor device performance. The first dielectric layer serves as a base layer, providing structural support and potentially acting as a barrier or interface layer. The second dielectric layer, being a monolayer, ensures minimal thickness while allowing for targeted implantation to achieve desired electrical properties. The implantation step may involve ions or other species to alter the monolayer's composition or structure, improving its functionality in semiconductor applications. This method is particularly useful in advanced semiconductor manufacturing where precise control of dielectric properties is essential for high-performance devices.
3. The method of claim 1, wherein the implanting the first dielectric layer and the implanting the second dielectric layer comprise implanting argon.
4. The method of claim 1, wherein the implanting the first dielectric layer and the implanting the second dielectric layer comprise implanting nitrogen.
5. The method of claim 1 further comprising, after the first dielectric layer is deposited and before the second dielectric layer is deposited, treating the first dielectric layer using hydrogen radicals, and wherein process gases for treating the first dielectric layer are free from silicon-containing precursors.
This invention relates to semiconductor manufacturing, specifically to a method for improving the quality of dielectric layers in integrated circuits. The problem addressed is the formation of defects or poor adhesion between sequentially deposited dielectric layers, which can degrade device performance and reliability. The method involves depositing a first dielectric layer on a substrate, followed by a treatment step using hydrogen radicals before depositing a second dielectric layer. The hydrogen radical treatment enhances the surface properties of the first dielectric layer, such as reducing surface roughness, removing contaminants, or improving adhesion. Importantly, the treatment process gases do not contain silicon-containing precursors, ensuring that no additional silicon is introduced during the treatment, which could alter the desired material properties. The first dielectric layer is deposited using a plasma-enhanced chemical vapor deposition (PECVD) process, where a silicon-containing precursor and an oxidizing gas are introduced into a reaction chamber. The hydrogen radical treatment is performed in the same chamber, using a plasma to generate hydrogen radicals from a hydrogen-containing gas. This treatment step modifies the surface of the first dielectric layer without depositing additional material, ensuring compatibility with subsequent processing steps. The second dielectric layer is then deposited on the treated surface, resulting in improved interface quality and overall device performance.
6. The method of claim 5 further comprising, after the second dielectric layer is deposited, further treating the second dielectric layer using additional hydrogen radicals.
This invention relates to semiconductor manufacturing, specifically to a method for treating dielectric layers in integrated circuit fabrication. The problem addressed is improving the quality and performance of dielectric layers, particularly in high-k metal gate (HKMG) structures, where defects or impurities can degrade device reliability and electrical properties. The method involves depositing a first dielectric layer on a substrate, followed by depositing a second dielectric layer over the first layer. After the second dielectric layer is deposited, it is treated with additional hydrogen radicals to enhance its properties. The hydrogen radical treatment may include exposing the second dielectric layer to a plasma or other hydrogen radical source to passivate defects, reduce impurities, or modify the layer's composition. This treatment step improves the dielectric layer's dielectric constant, leakage current characteristics, and overall reliability. The first dielectric layer may serve as a base layer or interface layer, while the second dielectric layer may be a high-k dielectric material, such as hafnium oxide or zirconium oxide. The hydrogen radical treatment is applied specifically to the second dielectric layer to optimize its electrical and structural properties. This method is particularly useful in advanced semiconductor devices where precise control of dielectric properties is critical for performance and yield.
7. The method of claim 1, wherein the implanting results in the first dielectric layer to have a more neutral stress.
8. The method of claim 1, wherein the implanting the first dielectric layer is performed using an energy in a range between about 1 keV and about 5 keV.
This invention relates to semiconductor manufacturing, specifically to a method of forming a dielectric layer on a substrate. The problem addressed is achieving precise control over the properties of dielectric layers during deposition, which is critical for modern semiconductor devices. The method involves implanting a first dielectric layer onto a substrate using a specific energy range to optimize layer characteristics. The process begins by depositing a dielectric layer onto a substrate, which may include materials like silicon, silicon dioxide, or other semiconductor materials. The dielectric layer is then implanted with ions or other species to modify its properties. The implantation energy is controlled within a range of approximately 1 keV to 5 keV to ensure uniform and precise modification of the dielectric layer. This energy range is selected to balance implantation depth and damage to the underlying substrate, ensuring optimal electrical and structural properties. The method may also include additional steps such as annealing or further deposition of dielectric layers to refine the material properties. The controlled implantation energy helps achieve desired dielectric constants, thickness uniformity, and defect density, which are essential for high-performance semiconductor devices. This technique is particularly useful in advanced node manufacturing where precise material properties are critical for device functionality and reliability.
12. The method of claim 11, wherein the hydrogen radicals are generated using a process gas, and wherein the process gas comprises hydrogen and is free from silicon and nitrogen.
17. The method of claim 10, wherein the first silicon nitride layer and the second silicon nitride layer are formed using same process gases.
18. The method of claim 17, wherein the first silicon nitride layer and the second silicon nitride layer are formed using same silicon-containing process gases.
19. The method of claim 10, wherein the first silicon nitride layer has a first stress with a first magnitude, and the second silicon nitride layer has a second stress with a second magnitude greater than the first magnitude.
This invention relates to semiconductor fabrication, specifically to stress engineering in silicon nitride layers to improve device performance. The problem addressed is the need for controlled stress in semiconductor structures to enhance mobility and performance of transistors, particularly in advanced integrated circuits. The method involves depositing a first silicon nitride layer with a first stress magnitude and a second silicon nitride layer with a second stress magnitude greater than the first. The first silicon nitride layer is deposited on a substrate, followed by the second silicon nitride layer. The stress difference between the two layers creates a strain effect in the underlying semiconductor material, which can enhance carrier mobility in transistors. The first silicon nitride layer may be deposited using a low-stress deposition process, while the second silicon nitride layer is deposited using a high-stress process, such as plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The stress in the second layer is greater than that in the first, allowing for fine-tuning of the strain effect. The method may also include patterning the layers to selectively apply stress to specific regions of the semiconductor device. This approach is particularly useful in strained silicon technologies, where controlled stress improves transistor performance by increasing electron and hole mobility.
20. The method of claim 19, wherein the first magnitude is smaller than about 0.2 GPa, and the second magnitude higher than about 1 GPa.
This invention relates to a method for processing a material, particularly for enhancing its mechanical properties through controlled stress application. The method addresses the challenge of achieving a material with both high strength and sufficient ductility, which is often difficult to attain simultaneously. The process involves applying a first stress to the material with a magnitude smaller than about 0.2 GPa, followed by applying a second stress with a magnitude higher than about 1 GPa. The first stress is applied to induce a specific deformation mechanism, such as dislocation movement or phase transformation, while the second stress further strengthens the material by introducing additional defects or refining its microstructure. The sequence and magnitude of the applied stresses are carefully controlled to balance strength and ductility, ensuring the material retains its structural integrity while improving its mechanical performance. This method is particularly useful in manufacturing high-performance alloys, composites, or other advanced materials where both strength and ductility are critical. The invention provides a way to tailor material properties by leveraging distinct stress-induced mechanisms at different stages of processing.
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July 20, 2020
November 15, 2022
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