Patentable/Patents/US-11502196
US-11502196

Stress modulation for dielectric layers

PublishedNovember 15, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

Patent Claims
12 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The method of claim 1, wherein the second dielectric layer is deposited on, and physically contacting, the first dielectric layer, wherein the second dielectric layer is a mono layer, and wherein the implanting the second dielectric layer is performed on the mono layer.

3

3. The method of claim 1, wherein the implanting the first dielectric layer and the implanting the second dielectric layer comprise implanting argon.

4

4. The method of claim 1, wherein the implanting the first dielectric layer and the implanting the second dielectric layer comprise implanting nitrogen.

5

5. The method of claim 1 further comprising, after the first dielectric layer is deposited and before the second dielectric layer is deposited, treating the first dielectric layer using hydrogen radicals, and wherein process gases for treating the first dielectric layer are free from silicon-containing precursors.

6

6. The method of claim 5 further comprising, after the second dielectric layer is deposited, further treating the second dielectric layer using additional hydrogen radicals.

7

7. The method of claim 1, wherein the implanting results in the first dielectric layer to have a more neutral stress.

8

8. The method of claim 1, wherein the implanting the first dielectric layer is performed using an energy in a range between about 1 keV and about 5 keV.

12

12. The method of claim 11, wherein the hydrogen radicals are generated using a process gas, and wherein the process gas comprises hydrogen and is free from silicon and nitrogen.

17

17. The method of claim 10, wherein the first silicon nitride layer and the second silicon nitride layer are formed using same process gases.

18

18. The method of claim 17, wherein the first silicon nitride layer and the second silicon nitride layer are formed using same silicon-containing process gases.

19

19. The method of claim 10, wherein the first silicon nitride layer has a first stress with a first magnitude, and the second silicon nitride layer has a second stress with a second magnitude greater than the first magnitude.

20

20. The method of claim 19, wherein the first magnitude is smaller than about 0.2 GPa, and the second magnitude higher than about 1 GPa.

Classification Codes (CPC)

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Patent Metadata

Filing Date

July 20, 2020

Publication Date

November 15, 2022

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Cite as: Patentable. “Stress modulation for dielectric layers” (US-11502196). https://patentable.app/patents/US-11502196

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