Patentable/Patents/US-11503238
US-11503238

Image sensor

PublishedNovember 15, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

An image sensor is provided. The image sensor includes a pixel array including first and second pixels, the first and second pixels receiving the same transfer gate signal and outputting first and second signal voltages, respectively, a transfer gate driver receiving first and second voltages and generating the transfer gate signal, the transfer gate signal having the first voltage as its maximum voltage and having the second voltage as its minimum voltage and a compensation module detecting a variation in the second voltage, generating a compensation voltage based on the variation in the second voltage, and performing a compensation operation.

Patent Claims
3 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 7

Original Legal Text

7. The image sensing device of claim 6, wherein the compensation module generates the compensated ramp signal based on a variation of transconductances of each the first bias transistor, the second bias transistor and the second bias PMOS transistor.

Plain English Translation

This invention relates to an image sensing device with improved signal compensation for accurate pixel readout. The device addresses the problem of signal distortion caused by variations in transistor transconductances during analog-to-digital conversion (ADC) in complementary metal-oxide-semiconductor (CMOS) image sensors. These variations can lead to inaccuracies in pixel signal representation, degrading image quality. The image sensing device includes a pixel array, a ramp signal generator, and a compensation module. The ramp signal generator produces a reference signal used for ADC, while the compensation module adjusts this signal to counteract distortions introduced by transistor transconductance variations. The compensation module specifically accounts for variations in three transistors: a first bias transistor, a second bias transistor, and a second bias PMOS transistor. These transistors influence the ramp signal's slope and linearity, which are critical for precise pixel value conversion. By dynamically compensating the ramp signal based on these transconductance variations, the device ensures consistent and accurate signal conversion across the pixel array. This compensation mechanism enhances the overall performance of the image sensor, particularly in applications requiring high precision, such as medical imaging or scientific instrumentation. The invention improves signal integrity without requiring complex calibration procedures, making it suitable for integration into existing CMOS image sensor designs.

Claim 9

Original Legal Text

9. The image sensing device of claim 8, wherein the compensation module generates the compensated ramp signal based on variations of transconductances of each the first bias NMOS transistor, the first bias PMOS transistor and the third bias PMOS transistor.

Plain English translation pending...
Claim 17

Original Legal Text

17. The operating method of claim 16, wherein the first bias transistor and the first NMOS transistor are enabled the amplified negative supply voltage.

Plain English Translation

This invention relates to electronic circuits, specifically to methods for operating bias transistors and NMOS transistors in a voltage amplification system. The problem addressed is the efficient control and amplification of negative supply voltages in integrated circuits, particularly in applications requiring precise voltage regulation and stability. The method involves enabling a first bias transistor and a first NMOS transistor to amplify a negative supply voltage. The bias transistor provides a stable reference current or voltage, while the NMOS transistor acts as a switching or amplification element. The amplified negative supply voltage is then used to drive other circuit components, ensuring proper operation in low-voltage or high-precision applications. The method may also include additional steps such as adjusting the bias current or voltage to optimize performance under varying load conditions. The invention ensures reliable voltage amplification while minimizing power consumption and noise, making it suitable for analog and mixed-signal integrated circuits.

Classification Codes (CPC)

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Patent Metadata

Filing Date

July 29, 2020

Publication Date

November 15, 2022

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