A semiconductor device includes a first n-type transistor and a first p-type transistor that are positioned side by side over a substrate. The first n-type transistor includes a first n-type source/drain (S/D) region, a first n-type channel region, and a second n-type S/D region that are formed based on a first continuous channel structure extending along a horizontal direction parallel to the substrate. The first n-type channel region is positioned between the first n-type S/D region and the second n-type S/D region. The first p-type transistor includes a first p-type S/D region, a first p-type channel region, and a second p-type S/D region that are formed based on the first continuous channel structure. The first p-type channel region is positioned between the first p-type S/D region and the second p-type S/D region. The second n-type S/D region is in contact with the first p-type S/D region.
Legal claims defining the scope of protection, as filed with the USPTO.
6. The semiconductor device of claim 1, wherein the first continuous channel structure comprises one of a nanowire and a nanosheet that is arranged along the horizontal direction and extend through the first n-type transistor and the first p-type transistor.
7. The semiconductor device of claim 1, wherein the first n-type transistor further comprises a first n-type gate layer that surrounds the first n-type channel region.
8. The semiconductor device of claim 1, wherein the first p-type transistor further comprises a first p-type gate layer that surrounds the first p-type channel region.
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December 16, 2020
November 22, 2022
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