A semiconductor device includes a first n-type transistor and a first p-type transistor that are positioned side by side over a substrate. The first n-type transistor includes a first n-type source/drain (S/D) region, a first n-type channel region, and a second n-type S/D region that are formed based on a first continuous channel structure extending along a horizontal direction parallel to the substrate. The first n-type channel region is positioned between the first n-type S/D region and the second n-type S/D region. The first p-type transistor includes a first p-type S/D region, a first p-type channel region, and a second p-type S/D region that are formed based on the first continuous channel structure. The first p-type channel region is positioned between the first p-type S/D region and the second p-type S/D region. The second n-type S/D region is in contact with the first p-type S/D region.
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6. The semiconductor device of claim 1, wherein the first continuous channel structure comprises one of a nanowire and a nanosheet that is arranged along the horizontal direction and extend through the first n-type transistor and the first p-type transistor.
This invention relates to semiconductor devices, specifically those incorporating advanced transistor structures for improved performance and scalability. The device addresses challenges in modern semiconductor manufacturing, such as maintaining high drive current and efficient switching in densely packed transistors while minimizing leakage and power consumption. The semiconductor device includes a first continuous channel structure, which may be either a nanowire or a nanosheet, oriented horizontally and extending through both an n-type transistor and a p-type transistor. This continuous structure allows for seamless integration of complementary transistors (n-type and p-type) within a single channel, enhancing device density and reducing parasitic resistance. The horizontal arrangement facilitates better control over channel dimensions and alignment, improving manufacturability and yield. The nanowire or nanosheet design enables superior electrostatic control, reducing short-channel effects and improving switching efficiency. This configuration is particularly useful in advanced logic circuits, such as CMOS (complementary metal-oxide-semiconductor) devices, where both n-type and p-type transistors are required in close proximity. The invention leverages existing semiconductor fabrication techniques, such as epitaxial growth and self-aligned patterning, to form the continuous channel structure while ensuring compatibility with high-volume manufacturing processes. The resulting device offers enhanced performance, scalability, and reliability for next-generation semiconductor applications.
7. The semiconductor device of claim 1, wherein the first n-type transistor further comprises a first n-type gate layer that surrounds the first n-type channel region.
8. The semiconductor device of claim 1, wherein the first p-type transistor further comprises a first p-type gate layer that surrounds the first p-type channel region.
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December 16, 2020
November 22, 2022
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