A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
3. The device of claim 2, wherein the first via and the second via are offset with respect to one another in both an X-direction and a Y-direction in a top view.
4. The device of claim 2, further comprising: a glue layer disposed on side surfaces and a bottom surface of the second via.
A semiconductor device includes a substrate with a first via and a second via formed in the substrate. The first via is filled with a conductive material, while the second via is hollow and lined with an insulating material. The second via is used to mechanically support the substrate during processing. The device further includes a glue layer applied to the side surfaces and the bottom surface of the second via. This glue layer enhances adhesion between the second via and surrounding materials, improving structural integrity and reliability. The conductive material in the first via provides electrical connectivity, while the hollow second via reduces stress and prevents cracking during thermal cycling. The glue layer ensures stable bonding, preventing delamination or failure under mechanical stress. This design is particularly useful in semiconductor packaging where thermal and mechanical stability are critical. The combination of conductive and hollow vias with an adhesive layer allows for robust interconnections while maintaining structural integrity.
5. The device of claim 4, wherein the glue layer contains titanium or titanium nitride.
6. The device of claim 1, wherein a first maximum lateral dimension of the laterally-protruding bottom portion is greater than a second maximum lateral dimension of the top portion.
7. The device of claim 1, wherein the source/drain contact and the first via have different metal material compositions.
A semiconductor device includes a source/drain contact and a first via, where the source/drain contact and the first via are composed of different metal materials. The device is designed to improve electrical performance and reliability in integrated circuits by optimizing the material properties of conductive pathways. The source/drain contact is typically formed in a semiconductor substrate and provides electrical connection to active regions, while the first via is a conductive interconnect feature that extends vertically to connect different metal layers. By using distinct metal compositions for these components, the device can enhance conductivity, reduce resistance, and mitigate issues like electromigration or thermal stress. The different materials may be selected based on their electrical conductivity, adhesion properties, and compatibility with surrounding materials. This design is particularly useful in advanced semiconductor nodes where performance and reliability are critical. The device may also include additional conductive features, such as a second via or a gate contact, which may further interact with the source/drain contact and the first via to form a complete electrical pathway. The use of different metal compositions allows for tailored optimization of each component, ensuring efficient signal transmission and long-term device stability.
8. The device of claim 1, wherein an uppermost surface of the source/drain contact is narrower than a bottommost surface of the first via.
The invention relates to semiconductor device fabrication, specifically addressing challenges in forming reliable electrical connections between source/drain regions and interconnect layers. A common issue in advanced semiconductor manufacturing is misalignment or poor contact between source/drain contacts and vias, which can degrade device performance or cause failures. The invention improves this by ensuring the uppermost surface of the source/drain contact is narrower than the bottommost surface of the first via. This design prevents over-etching during via formation, which could otherwise damage the underlying contact. The source/drain contact is formed in a semiconductor substrate and electrically connects to source/drain regions. The first via is part of an interconnect structure that extends vertically to connect to the source/drain contact. By making the via's bottom surface wider than the contact's top surface, the via can be formed with better alignment and reduced risk of exposure to the contact's sidewalls, which could lead to short circuits or weak connections. The invention also includes a dielectric layer surrounding the contact and via to insulate them from adjacent structures. This configuration enhances manufacturing yield and reliability in semiconductor devices, particularly in advanced nodes where feature sizes are extremely small.
9. The device of claim 1, wherein the laterally-protruding bottom portion is in direct contact with the source/drain contact.
13. The device of claim 11, wherein the source/drain via and the gate via are offset from each other in both a first horizontal direction and a second horizontal direction that is perpendicular to the first horizontal direction in a top view.
14. The device of claim 11, wherein the glue layer contains titanium or titanium nitride.
17. The device of claim 16, further comprising: a glue layer disposed on side surfaces and a bottom surface of the gate via, wherein the glue layer contains titanium or titanium nitride.
19. The device of claim 15, wherein a bottom surface of the source/drain via is in direct contact with a top surface of the source/drain contact.
20. The device of claim 15, wherein the top portion of the source/drain via is more slanted than the laterally-protruding bottom portion of the source/drain via in the cross-sectional side view.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 11, 2020
November 22, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.