A method for the nanoscale etching of a layer of Ge1-xSnx on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge1-xSnx using a mixture comprising dichlorine (Cl2) and dinitrogen (N2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge1-xSnx on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge1-xSnx according to the etching method. A conduction channel made of Ge1-xSnx for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge1-xSnx.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method according to claim 1, the etching pressure being lower than or equal to 5 mTorr.
3. The method according to claim 2, the etching pressure being lower than or equal to 2 mTorr for a concentration x of tin higher than or equal to 15%.
4. The method according to claim 1, the mixture further comprising dioxygen (O2).
5. The method according to claim 1, the step of removing consisting of an acid chemical attack, the acid preferably being hydrofluoric acid (HF) or hydrochloric acid (HCl).
6. The method according to claim 1, further comprising a step of depositing a mask on the layer of Ge1-xSnx, preferably a hard mask, for example a mask made of hydrogen silsesqwoxane (HSQ) resin, said deposition step coming before the step of plasma-etching the Ge1-xSnx.
7. The method according to claim 6, further comprising a step of removing the mask, said step of removing the mask coming after the step of plasma-etching the Ge1-xSnx.
9. The method according to claim 8, the carrier comprising a free surface, the free surface comprising a layer of Ge such that the layer of Ge1-xSnx is formed on the layer of Ge, the method further comprising a step of selectively plasma-etching the layer of Ge, said selective plasma-etching step preferably being performed using carbon tetrafluoride (CF4) and coming after the step of etching the Ge1-xSnx.
10. A conduction channel made of Ge1-xSnx for a FET transistor, the conduction channel being obtained according to the method of claim 8, the carrier comprising an etch bottom, the etch bottom around the etched layer of Ge1-xSnx being smooth, i.e. exhibiting a surface roughness lower than 2 nanometres, preferably lower than 0.5 nanometre.
11. The conduction channel made of Ge1-xSnx according to claim 10 forming horizontal fins arranged one above the other.
12. The conduction channel made of Ge1-xSnx according to claim 10 forming nanowires.
13. A FET transistor comprising a plurality of conduction channels made of Ge1-xSnx that are chosen according to claim 10.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 22, 2021
November 29, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.