In one embodiment, an apparatus includes a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include a multiplier circuit comprising a parallel combinatorial multiplier, and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The at least one computer readable storage medium of claim 1, wherein the 27-bit×411-bit parallel combinatorial multiplier of the multiplier circuit is to multiply the first 384-bit value and the second 384-bit value in 16 clock cycles.
5. The at least one computer readable storage medium of claim 1, wherein the method further comprises in response to determining that the modulus reduction operation is not to be performed according to the NIST prime value, performing the modulus reduction operation comprising a plurality of multiplication operations on a most significant portion of the first result.
8. The at least one computer readable storage medium of claim 7, wherein the method further comprises in response to determining that the most significant portion of the first result is not greater than the prime modulus, setting the reduction result equal to a most significant portion of the first result.
10. An apparatus according to claim 9, wherein the 27-bit×411-bit parallel combinatorial multiplier of the multiplier circuit is to multiply the first 384-bit value and the second 384-bit value in 16 clock cycles.
12. An apparatus according to claim 9, wherein the hardware accelerator is further to execute a Rivest Shamir Adleman (RSA) operation, wherein to execute the RSA operation comprises to use the 27-bit×411-bit parallel combinatorial multiplier of the multiplier circuit to multiply a third 384-bit value and a fourth 384-bit value.
14. An apparatus according to claim 13, wherein the ECC circuit comprises an elliptic curve (EC) scalar multiplier.
15. An apparatus according to claim 9, wherein, in response to determining that the modulus reduction operation is not to be performed according to the NIST prime value, the ECC circuit is to perform the modulus reduction operation comprising a plurality of multiplication operations on a most significant portion of the first result.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 8, 2021
November 29, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.