In one embodiment, an apparatus includes a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include a multiplier circuit comprising a parallel combinatorial multiplier, and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.
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2. The at least one computer readable storage medium of claim 1, wherein the 27-bit×411-bit parallel combinatorial multiplier of the multiplier circuit is to multiply the first 384-bit value and the second 384-bit value in 16 clock cycles.
The invention relates to high-speed cryptographic processing, specifically a parallel combinatorial multiplier circuit designed for efficient multiplication of large-bit values. The problem addressed is the computational inefficiency in cryptographic operations, particularly in multiplying large integers, which are common in encryption algorithms. Traditional serial multipliers are slow for such operations, while existing parallel multipliers often require excessive hardware resources or clock cycles. The invention provides a multiplier circuit with a 27-bit×411-bit parallel combinatorial multiplier that performs multiplication of two 384-bit values in 16 clock cycles. The multiplier circuit includes a plurality of 27-bit×411-bit multiplier units, each configured to generate partial products from the two 384-bit values. These partial products are then combined using a Wallace tree structure, which efficiently reduces the number of partial products through multiple stages of compression. The Wallace tree outputs are further processed by a carry-save adder tree, which accumulates the results into a final product. The circuit is optimized to minimize latency while maintaining high throughput, making it suitable for cryptographic applications requiring fast, large-bit multiplications. The design balances hardware complexity and performance, ensuring efficient execution of cryptographic operations.
5. The at least one computer readable storage medium of claim 1, wherein the method further comprises in response to determining that the modulus reduction operation is not to be performed according to the NIST prime value, performing the modulus reduction operation comprising a plurality of multiplication operations on a most significant portion of the first result.
The invention relates to cryptographic operations, specifically optimizing modulus reduction in modular arithmetic computations. The problem addressed is the computational inefficiency of modulus reduction when using large prime numbers, particularly those defined by the National Institute of Standards and Technology (NIST). Traditional modulus reduction methods can be slow, especially when dealing with large operands, leading to performance bottlenecks in cryptographic systems. The invention provides a method for performing modulus reduction that avoids unnecessary operations when the modulus reduction is not required according to a NIST prime value. Instead of performing a full modulus reduction, the method performs a plurality of multiplication operations on a most significant portion of the first result. This approach reduces computational overhead by focusing only on the relevant portion of the data, thereby improving efficiency without compromising security. The method is particularly useful in cryptographic applications where modular arithmetic is frequently used, such as in encryption, decryption, and digital signature algorithms. By selectively applying modulus reduction only when necessary, the invention enhances performance in systems relying on NIST-defined primes.
8. The at least one computer readable storage medium of claim 7, wherein the method further comprises in response to determining that the most significant portion of the first result is not greater than the prime modulus, setting the reduction result equal to a most significant portion of the first result.
The invention relates to cryptographic operations, specifically modular reduction in computing systems. The problem addressed is efficiently performing modular reduction, a critical operation in cryptographic algorithms, to ensure accurate and secure computations. The invention provides a method for reducing a numerical result modulo a prime modulus, particularly when the result is smaller than the modulus, to avoid unnecessary computational steps. The method involves determining whether the most significant portion of a first result exceeds a prime modulus. If the most significant portion is not greater than the prime modulus, the reduction result is set equal to the most significant portion of the first result. This avoids unnecessary reduction operations when the result is already within the desired range, improving computational efficiency. The method is implemented in a computer-readable storage medium, ensuring compatibility with various cryptographic systems. The invention optimizes modular reduction by dynamically adjusting the reduction process based on the magnitude of the result relative to the modulus. This approach reduces computational overhead in cryptographic operations, enhancing performance without compromising security. The method is particularly useful in applications requiring frequent modular arithmetic, such as encryption, decryption, and digital signatures.
10. An apparatus according to claim 9, wherein the 27-bit×411-bit parallel combinatorial multiplier of the multiplier circuit is to multiply the first 384-bit value and the second 384-bit value in 16 clock cycles.
The apparatus is a cryptographic processing system designed for high-speed modular multiplication, a critical operation in public-key cryptography. The system addresses the computational inefficiency of large-bit modular multiplication, which is a bottleneck in cryptographic algorithms like RSA and ECC. The apparatus includes a multiplier circuit with a 27-bit×411-bit parallel combinatorial multiplier that performs the multiplication of two 384-bit values. The multiplier is optimized to complete the operation in 16 clock cycles, significantly improving throughput compared to traditional serial or sequential multipliers. The design leverages parallel processing to break down the 384-bit multiplication into smaller, concurrent operations, reducing latency. The apparatus may also include additional components such as a modular reduction unit to handle the final modular operation, ensuring the result adheres to cryptographic standards. The system is particularly useful in hardware accelerators for cryptographic applications, where speed and efficiency are critical. The parallel combinatorial multiplier's architecture allows for high-performance execution while maintaining low power consumption, making it suitable for embedded systems and high-security environments.
12. An apparatus according to claim 9, wherein the hardware accelerator is further to execute a Rivest Shamir Adleman (RSA) operation, wherein to execute the RSA operation comprises to use the 27-bit×411-bit parallel combinatorial multiplier of the multiplier circuit to multiply a third 384-bit value and a fourth 384-bit value.
The invention relates to cryptographic hardware acceleration, specifically for performing large-scale modular arithmetic operations used in public-key cryptography. The problem addressed is the computational inefficiency of software-based implementations of cryptographic algorithms, particularly those involving large integer multiplications, such as those required for RSA (Rivest-Shamir-Adleman) operations. The apparatus includes a hardware accelerator with a specialized multiplier circuit designed to perform high-speed modular multiplication. The multiplier circuit features a 27-bit×411-bit parallel combinatorial multiplier, which enables efficient multiplication of large integers. In this specific configuration, the hardware accelerator is further adapted to execute RSA operations by utilizing the multiplier circuit to multiply two 384-bit values. The 27-bit×411-bit multiplier is structured to handle the multiplication of a 384-bit value (split into 27-bit segments) with another 384-bit value, ensuring fast and secure cryptographic computations. This design optimizes performance for cryptographic workloads, reducing latency and power consumption compared to general-purpose processors. The apparatus is particularly useful in secure communication systems, digital signatures, and encryption applications where fast and reliable RSA operations are required.
14. An apparatus according to claim 13, wherein the ECC circuit comprises an elliptic curve (EC) scalar multiplier.
The invention relates to error correction in data storage systems, specifically addressing the need for efficient and secure error correction in high-density storage devices. Traditional error correction codes (ECC) may be computationally intensive or vulnerable to certain types of errors, particularly in systems where data integrity is critical. The apparatus includes an ECC circuit designed to correct errors in stored data, with a focus on improving performance and reliability. The ECC circuit incorporates an elliptic curve (EC) scalar multiplier, a cryptographic component that enhances error detection and correction by leveraging mathematical properties of elliptic curves. This approach allows for more robust error handling compared to conventional methods, particularly in environments where data corruption risks are high. The elliptic curve scalar multiplier enables efficient computation of error correction operations, reducing latency and improving overall system reliability. The apparatus may be integrated into storage controllers, solid-state drives, or other data storage systems where secure and efficient error correction is essential. The use of elliptic curve cryptography in the ECC circuit provides a balance between computational efficiency and strong error correction capabilities, making it suitable for applications requiring high data integrity.
15. An apparatus according to claim 9, wherein, in response to determining that the modulus reduction operation is not to be performed according to the NIST prime value, the ECC circuit is to perform the modulus reduction operation comprising a plurality of multiplication operations on a most significant portion of the first result.
The apparatus is designed for efficient elliptic curve cryptography (ECC) operations, specifically addressing the computational overhead in modulus reduction during scalar multiplication. In ECC, scalar multiplication involves repeated point addition and doubling, often requiring modulus reduction to ensure intermediate results remain within the finite field defined by a prime modulus. The apparatus includes a circuit configured to perform modulus reduction operations, particularly when the modulus reduction is not required to follow the NIST prime value standard. Instead of performing a full modulus reduction, the circuit optimizes the process by executing a plurality of multiplication operations solely on the most significant portion of the intermediate result. This selective reduction reduces computational complexity and improves performance without compromising security. The apparatus may also include additional components for handling other ECC operations, such as point addition and doubling, ensuring compatibility with standard cryptographic protocols. The invention aims to enhance the efficiency of ECC implementations in hardware, particularly in resource-constrained environments where computational speed is critical.
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January 8, 2021
November 29, 2022
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