Patentable/Patents/US-11521675
US-11521675

Block-dependent cell source bounce impact reduction in non-volatile memory

PublishedDecember 6, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A data storage system includes a storage medium coupled to a storage controller via an electrical interface connected to a plurality of input/output (IO) pads of the storage medium. The storage medium receives a read or write instruction from the storage controller via the IO pads, associates the read or write instruction with memory cells of a first block of a first plane of a plurality of planes of the storage medium, and adjusts a word line voltage level or a source line voltage level for the first block of the first plane based on (i) a position of the first plane with respect to the IO pads of the storage medium and (ii) a position of the first block within the first plane.

Patent Claims
6 claims

Legal claims defining the scope of protection, as filed with the USPTO.

6

6. The data storage system of claim 1, wherein the driver adjustment circuitry is configured to cause the word line driver to adjust the word line voltage level by sending (i) an adjustment enable signal to the word line driver and (ii) an adjustment amount signal to the word line driver specifying an amount to increase the word line voltage level.

7

7. The data storage system of claim 1, wherein the driver adjustment circuitry is configured to cause the source line driver to adjust the source line voltage level by sending (i) an adjustment enable signal to the source line driver and (ii) an adjustment amount signal to the source line driver specifying an amount to decrease the source line voltage level.

12

12. The method of claim 8, wherein adjusting the word line voltage level includes sending (i) an adjustment enable signal to the word line driver and (ii) an adjustment amount signal to the word line driver specifying an amount to increase the word line voltage level.

13

13. The method of claim 8, wherein adjusting the source line voltage level includes sending (i) an adjustment enable signal to the source line driver and (ii) an adjustment amount signal to the source line driver specifying an amount to decrease the source line voltage level.

19

19. The data storage system of claim 14, wherein the means for adjusting the word line voltage level include means for sending (i) an adjustment enable signal to the word line driver and (ii) an adjustment amount signal to the word line driver specifying an amount to increase the word line voltage level.

20

20. The data storage system of claim 14, wherein the means for adjusting the source line voltage level include means for sending (i) an adjustment enable signal to the source line driver and (ii) an adjustment amount signal to the source line driver specifying an amount to decrease the source line voltage level.

Classification Codes (CPC)

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Patent Metadata

Filing Date

June 16, 2021

Publication Date

December 6, 2022

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Cite as: Patentable. “Block-dependent cell source bounce impact reduction in non-volatile memory” (US-11521675). https://patentable.app/patents/US-11521675

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