In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma etching process comprises applying pulsed bias voltage and RF voltage with pulsed power.
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2. The method of claim 1, wherein the low voltage is zero.
A method for controlling a power converter involves regulating the output voltage by adjusting a switching frequency of a power switch. The method includes monitoring the output voltage of the power converter and comparing it to a reference voltage. If the output voltage is higher than the reference, the switching frequency is increased to reduce the output voltage. If the output voltage is lower than the reference, the switching frequency is decreased to increase the output voltage. The switching frequency is adjusted based on a proportional-integral (PI) controller that processes the difference between the output voltage and the reference voltage. The method also includes setting a low voltage threshold, and if the output voltage falls below this threshold, the switching frequency is set to zero to stop power conversion. This ensures the power converter operates efficiently while preventing damage from excessive voltage deviations. The method is particularly useful in applications requiring precise voltage regulation, such as DC-DC converters in power supplies or renewable energy systems.
3. The method of claim 1, wherein a duty ratio of each of the pulsed bias voltage and the pulsed power is in a range from 70% to 90%.
This invention relates to a method for processing a substrate using pulsed bias voltage and pulsed power, addressing the challenge of optimizing plasma processing efficiency and uniformity. The method involves applying a pulsed bias voltage to the substrate and a pulsed power to a plasma source, where the duty ratio of each pulse is controlled within a specific range. The duty ratio, defined as the ratio of the pulse duration to the total period, is set between 70% and 90% for both the bias voltage and the power supply. This range ensures effective plasma density control while minimizing unwanted effects such as excessive heating or non-uniform processing. The pulsed operation helps stabilize plasma conditions, improving etching or deposition uniformity across the substrate. The method is particularly useful in semiconductor manufacturing, where precise control of plasma parameters is critical for high-quality film deposition or etching processes. By maintaining the duty ratio within the specified range, the method balances plasma stability and processing efficiency, leading to improved yield and performance in semiconductor fabrication.
4. The method of claim 1, wherein the high voltage is in a range from 200 V to 400 V and the low voltage is in a range from 100 V to 150 V.
This invention relates to a method for controlling a power conversion system, specifically addressing the challenge of efficiently managing voltage levels in high-power applications. The method involves switching between a high voltage state and a low voltage state to optimize energy transfer and system stability. The high voltage state operates within a range of 200 V to 400 V, while the low voltage state operates within a range of 100 V to 150 V. These voltage ranges are selected to balance power delivery efficiency with system safety and component stress. The method ensures smooth transitions between the two voltage states, preventing abrupt changes that could damage components or disrupt system performance. By dynamically adjusting between these predefined voltage levels, the system can adapt to varying load conditions while maintaining stable operation. This approach is particularly useful in applications requiring precise voltage regulation, such as industrial machinery, renewable energy systems, or electric vehicle charging infrastructure. The invention improves energy efficiency and reliability by avoiding excessive voltage fluctuations and ensuring optimal power conversion across different operating conditions.
5. The method of claim 1, wherein the high power is in a range from 1000 W to 1500 W and the low power is in a range from 300 W to 500 W.
This invention relates to a method for controlling power output in a system, particularly for optimizing energy efficiency and performance. The method involves dynamically adjusting power levels between a high power state and a low power state to balance energy consumption and operational demands. The high power state operates within a range of 1000 W to 1500 W, while the low power state operates within a range of 300 W to 500 W. The transition between these states is based on system requirements, such as workload or environmental conditions, to ensure efficient energy use without compromising performance. The method may include monitoring system parameters to determine when to switch between the high and low power states, ensuring optimal power distribution. This approach is particularly useful in applications where energy efficiency is critical, such as industrial machinery, data centers, or renewable energy systems. By maintaining power within these specified ranges, the method prevents excessive energy waste while sustaining necessary operational capabilities. The invention addresses the challenge of balancing power efficiency with performance demands in energy-intensive systems.
6. The method of claim 1, wherein the plasma process comprises supplying HBr gas and one or more noble gases.
This invention relates to plasma processing techniques, specifically for etching or modifying semiconductor materials. The method addresses challenges in achieving precise and controlled material removal or surface modification during plasma-based fabrication processes. Traditional plasma etching often suffers from issues such as poor selectivity, uneven etching rates, or damage to underlying layers, which can degrade device performance. The method involves a plasma process that includes supplying hydrogen bromide (HBr) gas along with one or more noble gases, such as helium, argon, or neon. The combination of HBr and noble gases enhances the plasma's reactivity and stability, improving etching uniformity and selectivity. The noble gases help stabilize the plasma discharge, while HBr provides reactive species that facilitate precise material removal. This approach is particularly useful in semiconductor manufacturing, where controlled etching of silicon, silicon dioxide, or other materials is critical for fabricating high-performance devices. The use of noble gases also reduces plasma-induced damage, ensuring better device reliability. The method can be applied in various plasma etching systems, including reactive ion etching (RIE) and inductively coupled plasma (ICP) systems, to achieve optimized etching performance.
7. The method of claim 6, wherein a flow ratio of the HBr gas and the one or more noble gases is in a range from 0.3 to 0.7.
This invention relates to a semiconductor etching process using a gas mixture containing hydrogen bromide (HBr) and one or more noble gases. The process addresses challenges in achieving precise and controlled etching of semiconductor materials, particularly in applications requiring high selectivity and uniformity. The method involves introducing a gas mixture into an etching chamber, where the mixture includes HBr and at least one noble gas, such as helium, neon, argon, krypton, or xenon. The noble gases enhance the etching process by improving plasma stability, reducing polymer deposition, and increasing etch rate uniformity. The flow ratio of HBr to the noble gases is carefully controlled within a specific range, from 0.3 to 0.7, to optimize etching performance. This ratio ensures efficient material removal while minimizing damage to underlying layers and maintaining process consistency. The method is particularly useful in advanced semiconductor manufacturing, where precise etching is critical for device performance and yield. The controlled gas mixture and flow ratio contribute to improved etch selectivity, reduced defect formation, and enhanced process repeatability.
8. The method of claim 1, wherein the plasma process is performed under a pressure in a range from 1 mTorr to 100 mTorr.
This invention relates to plasma processing techniques, specifically addressing the optimization of process conditions for improved material deposition or etching in semiconductor manufacturing. The method involves performing a plasma process within a controlled pressure range to enhance uniformity, efficiency, or quality of the resulting material layer. The plasma process operates under a pressure between 1 millitorr (mTorr) and 100 mTorr, which is critical for achieving desired plasma density, ion energy distribution, and reaction kinetics. This pressure range ensures stable plasma generation while minimizing unwanted side effects such as excessive ion bombardment or gas phase reactions. The method may be applied to various plasma-based processes, including physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma etching, where precise control of process parameters is essential for high-performance semiconductor devices. By operating within this specific pressure range, the technique improves process reproducibility, reduces defects, and enhances overall yield in semiconductor fabrication. The invention is particularly useful in advanced node manufacturing where tight process tolerances are required.
9. The method of claim 1, wherein a bottom of the recess has a W-shape or a wavy shape.
This invention relates to a method for forming a recess in a substrate, particularly for semiconductor or microelectronic applications. The problem addressed is the need for improved structural and electrical properties in recessed features, such as trenches or vias, by optimizing the shape of the recess bottom. The method involves etching a recess into a substrate, where the recess has a bottom surface with a W-shape or wavy contour. This non-planar bottom surface enhances mechanical stability, reduces stress concentrations, and improves adhesion for subsequent material deposition. The wavy or W-shaped bottom may be achieved through controlled etching processes, such as anisotropic or isotropic etching, or by combining multiple etching steps with different parameters. The recess may be used for forming transistors, capacitors, or interconnect structures in integrated circuits. The W-shaped or wavy bottom surface increases the surface area, which is beneficial for applications requiring high-capacity storage or improved contact interfaces. The method may also include additional steps such as cleaning, passivation, or deposition of conductive, insulating, or semiconducting materials into the recess. The resulting structure provides better performance in terms of electrical conductivity, thermal dissipation, and mechanical robustness compared to conventional flat-bottomed recesses.
10. The method of claim 1, wherein one cycle of the pulsed bias and the pulsed power having one high value time and one low value time is in a range from 0.5 sec to 20 sec.
This invention relates to a method for controlling pulsed bias and pulsed power in a plasma processing system, addressing the need for precise and efficient plasma generation and material processing. The method involves applying pulsed electrical bias and pulsed power to a plasma chamber, where the pulses are synchronized to enhance process stability and uniformity. Each cycle of the pulsed bias and pulsed power consists of a high value time and a low value time, with the total cycle duration ranging from 0.5 seconds to 20 seconds. This pulsed approach allows for better control over plasma density, ion energy, and process uniformity, improving etching, deposition, or other plasma-based processes. The method may include adjusting the duty cycle, frequency, or amplitude of the pulses to optimize performance for specific applications. The invention is particularly useful in semiconductor manufacturing, where precise plasma control is critical for high-yield production. By modulating the pulse timing within the specified range, the method ensures consistent plasma conditions, reducing defects and improving process repeatability.
12. The method of claim 11, wherein a depth of the shallow portion is in a range from 50 nm to 70 nm.
This invention relates to semiconductor fabrication, specifically to methods of forming shallow trench isolation (STI) structures in integrated circuits. The problem addressed is achieving precise control over the depth of shallow trench isolation features to ensure effective electrical isolation between adjacent devices while minimizing manufacturing variability. The method involves etching a substrate to form a trench with a shallow portion and a deeper portion. The shallow portion is formed to a specific depth range of 50 nm to 70 nm, which is critical for optimizing device performance and reliability. The deeper portion extends beyond this range to provide additional isolation depth where needed. The etching process may involve multiple steps, including a first etch to define the shallow portion and a second etch to extend the trench further into the substrate. The method may also include forming a liner or barrier layer within the trench to improve isolation properties and prevent defects. After etching, the trench is filled with an insulating material, such as silicon dioxide, to complete the isolation structure. The precise control of the shallow portion depth ensures consistent electrical isolation while maintaining structural integrity of the surrounding semiconductor material. This technique is particularly useful in advanced semiconductor nodes where tight dimensional control is essential for high-performance devices.
13. The method of claim 11, wherein a difference between a depth at deeper one of the deeper portions and a depth at the shallow portion is in a range from 0.5 nm to 5 nm.
This invention relates to semiconductor processing, specifically to methods of forming shallow trench isolation (STI) structures with controlled depth variations. The problem addressed is achieving precise depth control in STI trenches to improve device performance and reliability. The method involves etching a substrate to form trenches with deeper portions and shallower portions, where the depth difference between the deepest part of the deeper portions and the shallow portion is precisely controlled within a range of 0.5 nm to 5 nm. This controlled depth variation helps optimize electrical isolation while minimizing stress and defects in the semiconductor substrate. The etching process may include multiple steps, such as initial trench formation, selective deepening of certain regions, and subsequent shallow etching to refine the trench profile. The method ensures uniform isolation characteristics across the substrate, which is critical for advanced semiconductor devices where tight dimensional control is required. The invention is particularly useful in high-density integrated circuits where precise isolation is necessary to prevent leakage and crosstalk between adjacent devices. The depth control range specified ensures that the isolation structures do not excessively weaken the substrate while still providing effective electrical isolation.
14. The method of claim 11, wherein the plasma etching process comprises applying pulsed bias voltage changing between a high voltage and a low voltage lower than the high voltage and RF voltage with pulsed power changing between a high power and a low power lower than the high power.
This invention relates to plasma etching processes used in semiconductor manufacturing, specifically addressing challenges in achieving precise and uniform etching of materials. The method involves a plasma etching process that applies a pulsed bias voltage and radio frequency (RF) power to control the etching characteristics. The bias voltage alternates between a high voltage and a lower voltage, while the RF power also pulses between a high power and a lower power. This pulsed approach allows for better control over ion energy and flux, improving etching selectivity, uniformity, and profile control. The method is particularly useful for etching materials such as silicon, silicon dioxide, or other semiconductor materials where precise etching is critical. By modulating both the bias voltage and RF power in a synchronized manner, the process can minimize damage to underlying layers while achieving the desired etch depth and profile. This technique is applicable in various semiconductor fabrication steps, including patterning, trench formation, and via etching, where precise material removal is essential for device performance and yield. The pulsed nature of the voltage and power application helps in reducing unwanted side effects such as microloading and microtrenching, leading to more consistent and reliable etching results.
15. The method of claim 14, wherein, when the pulsed bias voltage is the high voltage, the pulsed power is the low power.
A method for controlling pulsed bias voltage and power in a semiconductor processing system addresses the challenge of optimizing plasma density and uniformity during etching or deposition processes. The method involves applying a pulsed bias voltage to a substrate, where the voltage alternates between a high voltage and a low voltage. When the pulsed bias voltage is at the high voltage level, the pulsed power supplied to the system is reduced to a low power level. This ensures that the high voltage does not excessively accelerate ions, which could damage the substrate or degrade process uniformity. Conversely, when the pulsed bias voltage is at the low voltage level, the pulsed power can be increased to a higher level to sustain plasma density. The method dynamically adjusts the power and voltage to balance ion energy and plasma density, improving process control and reducing defects. The system may include a power supply, a controller, and a substrate holder, where the controller modulates the power supply to achieve the desired voltage and power levels. This approach is particularly useful in advanced semiconductor manufacturing where precise control of plasma parameters is critical for yield and performance.
16. The method of claim 15, wherein a duty ratio of each of the pulsed bias and the pulsed power is in a range from 70% to 90%.
This invention relates to a method for controlling pulsed bias and pulsed power in a plasma processing system, specifically addressing the challenge of optimizing plasma density and uniformity during semiconductor fabrication. The method involves applying pulsed bias and pulsed power to a substrate in a plasma chamber, where the pulses are synchronized to enhance process efficiency and consistency. The pulsed bias is applied to the substrate to control ion energy, while the pulsed power is applied to the plasma source to regulate plasma density. The pulses are synchronized such that the pulsed bias is active during the off-phase of the pulsed power, ensuring precise control over ion bombardment and plasma generation. This synchronization prevents excessive ion energy during plasma ignition, improving uniformity and reducing damage to the substrate. The duty ratio of both the pulsed bias and pulsed power is maintained between 70% and 90%, balancing plasma stability and processing throughput. The method is particularly useful in etching and deposition processes where precise plasma control is critical. By adjusting the duty ratio within this range, the system achieves optimal plasma density and ion energy distribution, leading to higher yield and better device performance. The invention ensures efficient plasma processing while minimizing defects and variability in semiconductor manufacturing.
17. The method of claim 16, wherein at least one of the duty ratio of the pulsed bias and the duty ratio of the pulsed power changes during the recessing the source/drain regions.
This invention relates to semiconductor manufacturing, specifically to a method for recessing source/drain regions in a transistor structure. The problem addressed is controlling the etching process to achieve precise recess depths while minimizing damage to the surrounding material. The method involves applying pulsed bias and pulsed power to a plasma etching system during the recessing process. The duty ratios of these pulses can be adjusted dynamically to optimize etching performance. By varying the duty ratio of the pulsed bias or the pulsed power during etching, the method allows for better control over the recess depth and profile, reducing over-etching or under-etching. The pulsed bias and pulsed power are synchronized to enhance selectivity and uniformity. This approach improves the accuracy of source/drain recessing, which is critical for advanced semiconductor devices where precise dimensions are required. The dynamic adjustment of duty ratios ensures consistent etching rates and minimizes defects, leading to higher device yield and reliability. The method is particularly useful in finFET or nanowire transistor fabrication, where precise source/drain recessing is essential for optimal device performance.
19. The method of claim 14, wherein a pulse of the pulse bias voltage is synchronous with a pulse of the RF voltage.
A method for controlling a semiconductor processing system involves applying a pulse bias voltage to a substrate during plasma processing to enhance uniformity and efficiency. The method includes generating a radio frequency (RF) voltage to sustain a plasma within a processing chamber and applying a pulse bias voltage to the substrate to control ion energy and distribution. The pulse bias voltage is synchronized with the RF voltage to ensure precise timing and coordination between the plasma generation and substrate biasing. This synchronization improves process control, reduces plasma instability, and enhances uniformity in etching or deposition processes. The method may also include adjusting the pulse width, frequency, or amplitude of the pulse bias voltage to optimize performance for specific applications. By dynamically controlling the pulse bias voltage in sync with the RF voltage, the method achieves better process repeatability and efficiency in semiconductor manufacturing.
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November 25, 2020
December 6, 2022
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