In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma etching process comprises applying pulsed bias voltage and RF voltage with pulsed power.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein the low voltage is zero.
3. The method of claim 1, wherein a duty ratio of each of the pulsed bias voltage and the pulsed power is in a range from 70% to 90%.
4. The method of claim 1, wherein the high voltage is in a range from 200 V to 400 V and the low voltage is in a range from 100 V to 150 V.
5. The method of claim 1, wherein the high power is in a range from 1000 W to 1500 W and the low power is in a range from 300 W to 500 W.
6. The method of claim 1, wherein the plasma process comprises supplying HBr gas and one or more noble gases.
7. The method of claim 6, wherein a flow ratio of the HBr gas and the one or more noble gases is in a range from 0.3 to 0.7.
8. The method of claim 1, wherein the plasma process is performed under a pressure in a range from 1 mTorr to 100 mTorr.
9. The method of claim 1, wherein a bottom of the recess has a W-shape or a wavy shape.
10. The method of claim 1, wherein one cycle of the pulsed bias and the pulsed power having one high value time and one low value time is in a range from 0.5 sec to 20 sec.
12. The method of claim 11, wherein a depth of the shallow portion is in a range from 50 nm to 70 nm.
13. The method of claim 11, wherein a difference between a depth at deeper one of the deeper portions and a depth at the shallow portion is in a range from 0.5 nm to 5 nm.
14. The method of claim 11, wherein the plasma etching process comprises applying pulsed bias voltage changing between a high voltage and a low voltage lower than the high voltage and RF voltage with pulsed power changing between a high power and a low power lower than the high power.
15. The method of claim 14, wherein, when the pulsed bias voltage is the high voltage, the pulsed power is the low power.
16. The method of claim 15, wherein a duty ratio of each of the pulsed bias and the pulsed power is in a range from 70% to 90%.
17. The method of claim 16, wherein at least one of the duty ratio of the pulsed bias and the duty ratio of the pulsed power changes during the recessing the source/drain regions.
19. The method of claim 14, wherein a pulse of the pulse bias voltage is synchronous with a pulse of the RF voltage.
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November 25, 2020
December 6, 2022
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