Patentable/Patents/US-11526441
US-11526441

Hybrid memory systems with cache management

PublishedDecember 13, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

In a general aspect, a hybrid memory system with cache management is disclosed. In some aspects, a memory module includes volatile memory, non-volatile memory, and an internal cache. The internal cache is communicably coupled with the volatile memory and the non-volatile memory. Whether to execute a memory access request is determined by operation of the memory module. In response to the inability of the memory access request to be executed, a data transferring process is performed to copy data between the volatile memory and the non-volatile memory via the internal cache.

Patent Claims
1 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 12

Original Legal Text

12. The memory module of claim 11, wherein the first volatile memory comprises dynamic random-access memory (DRAM) and the second volatile memory comprises static random-access memory (SRAM).

Plain English Translation

This invention relates to a memory module designed to optimize data storage and retrieval in computing systems. The module addresses the challenge of balancing performance and power efficiency by integrating different types of volatile memory. The module includes a first volatile memory and a second volatile memory, each serving distinct roles in data handling. The first volatile memory is configured to store data in a high-density, cost-effective format, while the second volatile memory is optimized for low-latency access. The module further includes a controller that manages data transfer between the two memory types, ensuring efficient operation. The first volatile memory is implemented using dynamic random-access memory (DRAM), which provides high storage capacity at lower cost but requires periodic refreshing to retain data. The second volatile memory is implemented using static random-access memory (SRAM), which offers faster access times and does not require refreshing, making it ideal for high-speed operations. The controller coordinates data movement between DRAM and SRAM based on access patterns, prioritizing frequently accessed data in SRAM to reduce latency while maintaining overall system efficiency. This design enhances performance for applications requiring both large storage capacity and rapid data access.

Classification Codes (CPC)

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Patent Metadata

Filing Date

May 17, 2021

Publication Date

December 13, 2022

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