An under voltage lockout circuit includes a reference circuit, an oscillator, a voltage divider, and a dynamic comparator. The reference circuit generates a reference voltage signal and a current source activation signal. The oscillator is activated to generate a clock signal after receiving the current source activation signal. The voltage divider samples an operating voltage signal to generate a detection voltage signal after receiving the clock signal. The voltage divider includes a switched-capacitor circuit for adjusting a ratio of the detection voltage signal to the operating voltage signal. The dynamic comparator receives the clock signal, the detection voltage signal and the reference voltage signal, and compares the reference voltage signal with the detection voltage signal only after receiving the clock signal. When the reference voltage signal is higher than the detection voltage signal, the dynamic comparator outputs a power-on-reset pulse signal.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The under voltage lockout circuit according to claim 1, wherein the current generating circuit is a constant transduction circuit.
3. The under voltage lockout circuit according to claim 1, wherein the reference voltage generating circuit is a bandgap reference circuit.
4. The under voltage lockout circuit according to claim 1, wherein the voltage divider is a switched-capacitor circuit configured to adjust a ratio of the detection voltage signal to the operating voltage signal.
5. The under voltage lockout circuit according to claim 1, wherein when the reference voltage signal is not higher than the detection voltage signal, the dynamic comparator is maintained at an off state.
6. The under voltage lockout circuit according to claim 1, wherein the voltage divider is activated later than activation of the oscillator.
7. The under voltage lockout circuit according to claim 1, wherein the dynamic comparator is activated later than activation of the oscillator.
9. The under voltage lockout circuit according to claim 8, wherein when the reference voltage signal is not higher than the detection voltage signal, the dynamic comparator is maintained at an off state.
11. The method of generating the power-on-reset pulse signal according to claim 10, wherein when the detection voltage signal is not higher than the reference voltage signal, maintaining the dynamic comparator at an off state.
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August 13, 2021
December 13, 2022
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