This disclosure describes a memory cell array with enhanced read sensing margin. The memory cell array includes a write port and a read port being connected through first and second data storage lines. The memory cell array further includes multiple word lines and bit lines arranged in rows and columns such that the read port is coupled to a read word line, a read bit line, and a virtual ground. The read port includes a first transistor coupled to at least the read bit line and the virtual ground, a second transistor coupled to at least the first data storage line and the first transistor, a third transistor coupled to at least the second data storage line and the read word line, and a fourth transistor coupled at least the first data storage line and the read word line.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The memory cell array of claim 1, wherein the write port is configured to store a data value, the first data storage line is configured to carry the data value to the read port, and the second data storage line is configured to carry a complement of the data value to the read port.
3. The memory cell array of claim 1, where in the virtual ground is operatively connected to the read word line through an inverter.
4. The memory cell array of claim 1, wherein the first data storage line is connected to a gate terminal of the second transistor and a gate terminal of the fourth transistor.
5. The memory cell array of claim 1, wherein the second data storage line is connected to a gate terminal of the third transistor.
6. The memory cell array of claim 1, wherein the read bit line is further coupled to an inverter and the output of the inverter is accessible for a memory read operation.
7. The memory cell array of claim 1, wherein the read word line is connected to a shared source/drain terminal of the third and the fourth transistors.
8. The memory cell array of claim 1, wherein a gate terminal of the first transistor is connected to a shared source/drain terminal of the second, third, and fourth transistors.
9. The memory cell array of claim 1, wherein the first transistor is connected to the read bit line through a source/drain terminal and connected to the virtual ground through another source/drain terminal.
12. The memory device of claim 10, wherein the first data storage line is connected to a gate terminal of a first transistor and a gate terminal of a second transistor in the read port of the first bit cell.
13. The memory device of claim 12, wherein the second data storage line is connected to a gate terminal of a third transistor in the read port of the first bit cell.
14. The memory device of claim 10, wherein the read word line is connected to a shared source/drain terminal of first and second transistors in the read port of the first bit cell.
15. The memory device of claim 10, wherein the read port of the first bit cell is connected to the read bit line through a source/drain terminal of a first transistor in the read port of the first bit cell and connected to the virtual ground through another source/drain terminal of the first transistor in the read port of the first bit cell.
16. The memory device of claim 15, wherein a gate terminal of the first transistor in the read port of the first bit cell is connected to a shared source/drain terminal of second, third, and fourth transistors in the read port of the first bit cell.
17. The memory device of claim 10, wherein the read bit line is further coupled to an inverter and the output of the inverter is accessible for a memory read operation.
19. The method of claim 18, wherein operating the memory cell array comprises passing the data value in the write port to the read port through a data storage line and a complementary data storage line.
20. The method of claim 18, wherein setting the virtual ground comprises: setting the virtual ground to a logic value of ‘0’ in response to a selection of a bit cell of the memory cell array.
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September 18, 2020
December 20, 2022
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