An N-bit non-volatile multi-level memory cell (MLC) can include a lower electrode and an upper electrode spaced above the lower electrode. N ferroelectric material layers can be vertically spaced apart from one another between the lower electrode and the upper electrode, wherein N is at least 2 and at least one dielectric material layer having a thickness of less than 20 nm can be located between the N ferroelectric material layers.
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2. The N-bit non-volatile multi-level memory cell of claim 1 wherein N is equal to 2 providing a first ferroelectric material layer and a second ferroelectric material layer and the at least one dielectric material layer has a thickness of about 1 nm.
3. The N-bit non-volatile multi-level memory cell of claim 2 wherein the first ferroelectric material layer and a second ferroelectric material layer comprise ZrO2.
4. The N-bit non-volatile multi-level memory cell of claim 3 wherein the first ferroelectric material layer has a thickness of about 1 nm and a second ferroelectric material layer has a thickness of about 1 nm.
5. The N-bit non-volatile multi-level memory cell of claim 2 wherein the first ferroelectric material layer comprises HfO2 and the second ferroelectric material layer comprises HfO2.
6. The N-bit non-volatile multi-level memory cell of claim 1 wherein N is equal to 2 providing a first ferroelectric material layer and a second ferroelectric material layer and the at least one dielectric material layer has a thickness of about 5 nm.
7. The N-bit non-volatile multi-level memory cell of claim 6 wherein the first ferroelectric material layer and a second ferroelectric material layer comprise ZrO2 and are located on opposite surfaces of the at least one dielectric material layer.
8. The N-bit non-volatile multi-level memory cell of claim 7 wherein the first ferroelectric material layer has a thickness of about 1 nm and a second ferroelectric material layer has a thickness of about 1 nm.
9. The N-bit non-volatile multi-level memory cell of claim 6 wherein the first ferroelectric material layer comprises HfO2 and the second ferroelectric material layer comprises HfO2.
15. The N-bit non-volatile multi-level memory cell of claim 1 wherein the vertical stack of material layers provides a multi-peak Ec distribution wherein each peak in the multi-peak Ec distribution provides a respective data bit in the MLC.
16. The N-bit non-volatile multi-level memory cell of claim 15 wherein each of the peaks in the multi-peak Ec distribution is non-overlapping.
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September 25, 2020
December 20, 2022
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