Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency (RF) ICs.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The IC of claim 1, wherein a portion of one of the plurality of polysilicon dummies is above a portion of the central region of one of the plurality of diffusion dummies in a vertical direction orthogonal to the horizontal plane.
3. The IC of claim 2, wherein the one of the plurality of polysilicon dummies is aligned, in the vertical direction, above the one of the plurality of diffusion dummies.
4. The IC of claim 3, wherein the one of the plurality of polysilicon dummies is centered, in the vertical direction, above the one of the plurality of diffusion dummies.
5. The IC of claim 3, wherein an area of the central region of the one of the plurality of diffusion dummies corresponds to the one of the plurality of polysilicon dummies.
6. The IC of claim 1, wherein the perimeter region comprising the semiconductor material comprising the second resistivity extends around an entire perimeter of the semiconductor island.
7. The IC of claim 1, wherein the perimeter region comprising the semiconductor material comprising the second resistivity extends continuously around a perimeter of the semiconductor island.
8. The IC of claim 1, wherein the second resistivity is less than the first resistivity.
9. The IC of claim 1, wherein a difference in resistivity between the first resistivity and the second resistivity is due to a difference in dopant concentration between the central region and the perimeter region of the semiconductor island.
10. The IC of claim 1, wherein a difference in resistivity between the first resistivity and the second resistivity is due to a salicide on the perimeter region of the semiconductor island.
13. The method of claim 12, wherein treating the diffusion layer and the polysilicon layer comprises doping the plurality of diffusion dummies and the plurality of polysilicon dummies with an N-type dopant or a P-type dopant to increase dopant concentrations of the plurality of diffusion dummies and the plurality of polysilicon dummies.
14. The method of claim 12, wherein treating the diffusion layer and the polysilicon layer comprises applying a salicide to the plurality of diffusion dummies and the plurality of polysilicon dummies.
16. The method of claim 15, wherein applying the treatment from the vertical direction to the perimeter region of the one of the plurality of diffusion dummies further comprises applying the treatment to the perimeter region extending continuously around a perimeter of the one of the plurality of diffusion dummies.
17. The method of claim 15, wherein h central region of the one of the plurality of diffusion dummies below the one of the plurality of polysilicon dummies in the vertical direction is not exposed to the applied treatment.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 7, 2021
December 20, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.