A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.
Legal claims defining the scope of protection, as filed with the USPTO.
4. The memory circuit of claim 1, further comprising a third sense amplifier configured, during a portion of a second clock cycle, to perform a write operation including changing the state of the memory cell via the single port.
9. The memory circuit of claim 1, wherein the first sense amplifier is configured to perform consecutive read operations during a second clock cycle.
14. The method of claim 11, further comprising, during a portion of a second clock cycle, performing a write operation via a third sense amplifier including changing the state of the memory cell via the single port.
19. The method of claim 11, further comprising performing consecutive read operations during a second clock cycle via the first sense amplifier.
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May 30, 2021
January 3, 2023
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