An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extent and a second longitudinal extent. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first longitudinal extent and the second longitudinal extent, a first subfin portion under the upper fin portion in the first longitudinal extent having a first lateral dimension, and a second subfin portion under the upper fin portion in the second longitudinal extent having a second lateral dimension different than the first lateral dimension. The second subfin may be used in a drain extension region of a laterally-diffused metal-oxide semiconductor (LDMOS) device. The second subfin reduces subfin current and improves HCI reliability, regardless of the type of LDMOS device.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The IC structure of claim 1, wherein the second lateral dimension is less than the first lateral dimension.
3. The IC structure of claim 2, wherein the second subfin portion has inwardly curved outer surfaces.
4. The IC structure of claim 1, wherein each subfin portion is within a trench isolation, wherein the trench isolation has a bulbous cross-sectional shape adjacent the second subfin portion.
5. The IC structure of claim 1, wherein the second subfin portion is within a drain extension region of a fin-type laterally-diffused metal oxide semiconductor (LDMOS) device.
6. The IC structure of claim 5, wherein a portion of the first subfin portion is within the drain extension region.
7. The IC structure of claim 5, wherein the LDMOS device includes a first gate structure over the semiconductor fin and a second, floating gate structure over the drain extension region.
8. The IC structure of claim 5, wherein the LDMOS device includes a trench isolation in an n-well within the drain extension region and adjacent to the drain region.
9. The IC structure of claim 1, wherein the semiconductor fin includes a plurality of fins.
11. The FinFET LDMOS device of claim 10, wherein the second lateral dimension is less than the first lateral dimension.
12. The FinFET LDMOS device of claim 10, wherein the second subfin portion has inwardly curved outer surfaces.
13. The FinFET LDMOS device of claim 10, wherein each subfin portion is within a trench isolation, wherein the trench isolation has a bulbous cross-sectional shape adjacent the second subfin portion.
14. The FinFET LDMOS device of claim 10, wherein a portion of the first subfin portion is within the drain extension region.
15. The FinFET LDMOS device of claim 10, further comprising a second, floating gate structure spaced from the first gate structure, wherein the second, floating gate structure is over the drain extension region.
16. The FinFET LDMOS device of claim 10, further comprising a trench isolation in the n-well within the drain extension region and adjacent to the drain region.
19. The method of claim 18, wherein the dielectric adjacent the second subfin portion has a bulbous cross-sectional shape.
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July 2, 2020
January 3, 2023
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