Patentable/Patents/US-11551066
US-11551066

Deep neural networks (DNN) hardware accelerator and operation method thereof

PublishedJanuary 10, 2023
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.

Patent Claims
14 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The DNN hardware accelerator according to claim 1, wherein the bandwidth proportions of the target data size are obtained from dynamically analyzing the target data size by a microprocessor and sent to the network distributor.

3

3. The DNN hardware accelerator according to claim 1, wherein the bandwidth proportions of the target data size are associated with individual weights of the data types of the target data size.

6

6. The DNN hardware accelerator according to claim 1, wherein the input data received by the network distributor is from a buffer or from a memory connected through a system bus.

7

7. The DNN hardware accelerator according to claim 1, wherein when the target data size comprises a plurality of data layers, the data layers have different bandwidth proportions, and the network distributor allocates different individual bandwidths for the data layers.

8

8. The DNN hardware accelerator according to claim 1, wherein when the target data size comprises a plurality of data layers, the data layers have the same bandwidth proportions, and the network distributor allocates the same individual bandwidths for the data layers.

10

10. The operation method according to claim 9, wherein the step of analyzing, the step of configuring the bandwidth proportions and the step of determining are dynamically performed by a microprocessor.

11

11. The operation method according to claim 9, wherein the step of analyzing, the step of configuring the bandwidth proportions and the step of determining are achieved in an offline manner.

13

13. The operation method according to claim 9, wherein when the target data size comprises a plurality of data layers, different bandwidth proportions are configured for the data layers.

14

14. The operation method according to claim 9, wherein when the target data size comprises a plurality of data layers, the same bandwidth proportions are configured for the data layers.

17

17. The DNN hardware accelerator according to claim 15, wherein when the target data size comprises a plurality of data layers, the bandwidth and utilization analysis unit configures different individual transmission bandwidths for the data layers.

18

18. The DNN hardware accelerator according to claim 15, wherein when the target data size comprises a plurality of data layers, the bandwidth and utilization analysis unit configures the same individual transmission bandwidths for the data layers.

20

20. The operation method according to claim 19, wherein the bandwidth proportions of the target data size are obtained by dynamically analyzing the target data size and are sent to the network distributor.

21

21. The operation method according to claim 19, wherein the bandwidth proportions of the target data size are associated with individual weights of the data types of the target data size.

24

24. The operation method according to claim 19, wherein the input data received by the network distributor is from a buffer or from a memory connected through a system bus.

Classification Codes (CPC)

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Patent Metadata

Filing Date

January 15, 2019

Publication Date

January 10, 2023

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