A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The memory device of claim 1, wherein the thermal path structure includes a thermally conductive wall located in the top tier.
3. The memory device of claim 2, wherein a material of the thermally conductive wall is substantially the same as a material of the TCVs.
4. The memory device of claim 2, wherein a material of the thermally conductive wall is different from a material of the TCVs.
5. The memory device of claim 1, wherein the thermal path structure includes a dummy die located in the top tier and thermally conductive vias (TCVs) located on the middle tier and the bottom tier.
6. The memory device of claim 5, wherein the dummy die is made of a semiconductor material, and the semiconductor material of the dummy die is different from a material of the TCVs.
7. The memory device of claim 2, wherein the semiconductor chips in the middle tier are vertically stacked with the semiconductor chips in the bottom tier.
8. The memory device of claim 7, wherein the semiconductor chips in the top tier are spaced apart with a first distance, the semiconductor chips in the middle tier are spaced apart with a second distance, the semiconductor chips in the bottom tier are spaced apart with a third distance, the first distance is smaller than the second distance and the third distance.
10. The memory device of claim 9, wherein each of the thermal path structures includes a thermally conductive wall located in the top tier.
11. The memory device of claim 10, wherein a material of the thermally conductive wall includes silver paste, and a material of the TCVs includes copper or copper alloys.
12. The memory device of claim 10, wherein a material of the thermally conductive wall is substantially the same as a material of the TCVs and includes copper or copper alloys.
13. The memory device of claim 9, wherein the base chip is a semiconductor chip and the molding compound does not cover sidewalls of the base chip.
14. The memory device of claim 13, wherein the base chip includes a logic chip.
15. The memory device of claim 9, wherein each of the thermal path structures includes a semiconductor material dummy die located in the top tier.
16. The memory device of claim 15, wherein a material of the semiconductor material dummy die includes silicon, and a material of the TCVs includes copper or copper alloys.
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June 10, 2020
January 10, 2023
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