A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor package of claim 1, wherein a diameter of the via pattern is 40% or less of a width of the pad pattern.
3. The semiconductor package of claim 1, wherein a width of the pad pattern is within a range of 150 μm to 500 μm, and a diameter of the via pattern is within a range of 50 μm to 200 μm.
4. The semiconductor package of claim 1, wherein the pad pattern is a rectangular pad having a first side and a second side, and the center line passes a midpoint of the second side of the pad pattern.
5. The semiconductor package of claim 4, wherein at least three via patterns are along an extending direction of the first side and are spaced apart from each other.
6. The semiconductor package of claim 5, wherein a spacing distance in the extending direction of the first side between the via patterns is within a range of 250 μm to 450 μm.
7. The semiconductor package of claim 1, wherein the pad pattern has a dimple in an upper portion of the via pattern.
8. The semiconductor package of claim 7, wherein at least one of the conductive pastes has a void above the dimple.
9. The semiconductor package of claim 1, wherein the redistribution wiring layer further includes a solder ball pad exposed from the outer surface of the redistribution wiring layer.
10. The semiconductor package of claim 9, wherein a diameter of the solder ball pad is greater than a width of the pad pattern.
12. The semiconductor package of claim 11, wherein the width of the pad pattern is within a range of 150 μm to 500 μm, and the diameter of the via pattern is within a range of 50 μm to 200 μm.
13. The semiconductor package of claim 11, wherein the pad pattern is a rectangular pad having a first side and a second side, and the center line passes a midpoint of the second side of the pad pattern.
14. The semiconductor package of claim 13, wherein at least three via patterns are along an extending direction of the first side and are spaced apart from each other.
15. The semiconductor package of claim 14, wherein a spacing distance in the extending direction of the first side between the via patterns is within a range of 250 μm to 450 μm.
16. The semiconductor package of claim 11, wherein a spacing distance between the via pattern of one of the capacitor pads and the via pattern of the other one of the capacitor pads is within a range of 130 μm to 300 μm.
17. The semiconductor package of claim 11, wherein the pad pattern has a dimple in an upper portion of the via pattern.
18. The semiconductor package of claim 17, wherein at least one of the conductive pastes has a void above the dimple.
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June 9, 2021
January 10, 2023
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