A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein the substrate is formed as printed circuit board (PCB) having a plurality of pads configured for a plurality of conductive connections with the packaged semiconductor device in a surface mounted arrangement, the first conductive connection included in the plurality of conductive connections.
3. The method of claim 2, wherein the conductive connections in the plurality of conductive connections are orthogonally arranged in rows and columns.
4. The method of claim 1, wherein forming the isolation structure comprises reflowing a first group of solder balls configured and arranged to prevent the underfill material from contacting the first conductive connection, the first group of solder balls connected to a ground supply terminal at the substrate.
5. The method of claim 4, wherein the first group of solder balls connected to the ground supply terminal is further configured and arranged to provide electrical shielding for the first conductive connection.
6. The method of claim 1, wherein forming the isolation structure comprises depositing a barrier material configured and arranged to prevent the underfill material from reaching a region between the packaged semiconductor device and the substrate, the first conductive connection located within the region.
7. The method of claim 6, wherein the deposited barrier material is removed after dispensing the underfill material between the packaged semiconductor device and the substrate.
8. The method of claim 1, wherein the first conductive connection is configured for receiving or transmitting a radio frequency (RF) signal.
9. The method of claim 1, wherein the underfill material is characterized as a polymer material having a coefficient of thermal expansion (CTE) range compatible with a solder CTE range.
11. The method of claim 10, wherein forming the isolation structure comprises reflowing a first group of solder balls configured and arranged to prevent the underfill material from reaching the second region between the packaged semiconductor device and the substrate, the first group of solder balls connected to a ground supply terminal at the substrate.
12. The method of claim 11, wherein the first group of solder balls connected to the ground supply terminal is further configured and arranged to provide electrical shielding for the at least one conductive connection.
13. The method of claim 10, wherein forming the isolation structure comprises depositing a barrier material configured and arranged to prevent the underfill material from reaching the second region between the packaged semiconductor device and the substrate.
14. The method of claim 13, wherein the deposited barrier material is removed after dispensing the underfill material at the first region between the packaged semiconductor device and the substrate.
15. The method of claim 10, wherein the conductive connections in the plurality of conductive connections are orthogonally arranged in rows and columns.
16. The method of claim 10, wherein the at least one conductive connection is configured for receiving or transmitting a radio frequency (RF) signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 31, 2019
January 17, 2023
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