A semiconductor structure includes a multilayer structure having a first layer and a second layer disposed on the first layer. The semiconductor structure further includes at least a first via extending from a top of the second layer to a top of a first metal contact disposed in the first layer. A polymer film is disposed on at least a portion of sidewalls of the first via.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor structure of claim 1, wherein the first layer comprises a silicon substrate and the second layer comprises a dielectric layer.
3. The semiconductor structure of claim 1, further comprising a capping layer disposed between the first layer and the second layer.
5. The semiconductor structure of claim 4, wherein the first via, the second via and the first trench form a chamfer having a high chamfering angle.
6. The semiconductor structure of claim 1, wherein the multilayer structure further comprises a third layer disposed on the second layer, the third layer comprising an organic polymer layer.
7. The semiconductor structure of claim 1, wherein the first metal contact comprises one of tungsten, copper, and ruthenium.
8. The semiconductor structure of claim 1, wherein the polymer- oxide layer is a polymer-oxide layer derived from an etchant consisting of an argon gas etchant or a combination of an argon gas etchant and a helium gas etchant.
10. The integrated circuit of claim 9, wherein the first layer comprises a silicon substrate and the second layer comprises a dielectric layer.
11. The integrated circuit of claim 9, further comprising a capping layer disposed between the first layer and the second layer.
13. The integrated circuit of claim 12, wherein the first via, the second via and the first trench form a chamfer having a high chamfering angle.
14. The integrated circuit of claim 9, wherein the first metal contact comprises one of tungsten, copper, and ruthenium.
15. The integrated circuit of claim 9, wherein the polymer-oxide layer is a polymer-oxide layer derived from an etchant consisting of an argon gas etchant or a combination of an argon gas etchant and a helium gas etchant.
16. The integrated circuit of claim 12, further comprising a metal layer disposed in the first via, the second via and the first trench.
17. The integrated circuit of claim 9, wherein the polymer-oxide layer has a thickness of 1 to 3 nanometers.
18. The integrated circuit of claim 9, wherein the first layer is a silicon substrate and the second layer is a dielectric layer.
19. The semiconductor structure of claim 1, wherein the polymer-oxide layer has a thickness of 1 to 3 nanometers.
20. The semiconductor structure of claim 1, wherein the first layer is a silicon substrate and the second layer is a dielectric layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 29, 2019
January 17, 2023
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