A test circuit includes a comparator and a comparison control circuit. The comparator is configured to compare a first input signal with a second input signal to generate a comparison result signal. The comparison control circuit is configured to perform at least one of an operation for latching the comparison result signal as reference data and an operation for outputting the comparison result signal as a first output signal. The comparison control circuit is configured to provide expectation data as the first input signal and read data as the second input signal in accordance with the reference data.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The test circuit of claim 1, wherein the comparison control circuit is configured to provide the expectation data as the first input signal and the read data as the second input signal when the reference data has a pass determination level.
3. The test circuit of claim 1, wherein the comparison control circuit is configured to latch the comparison result signal as the reference data when a clock enable signal has a first level.
4. The test circuit of claim 3, wherein the comparison control circuit is configured to output the comparison result signal as the first output signal when the clock enable signal has a second level.
7. The semiconductor device of claim 6, wherein the comparison control circuit is configured to output the first output signal having the pass determination level regardless of the expectation data and the read data when the reference data has the fail determination level.
8. The semiconductor device of claim 7, wherein the comparison control circuit is configured to provide the expectation data as the first input signal and the read data as the second input signal when the reference data has a pass determination level.
9. The semiconductor device of claim 6, wherein the comparison control circuit is configured to latch the comparison result signal as the reference data when a clock enable signal has a first level.
10. The semiconductor device of claim 9, wherein the comparison control circuit is configured to output the comparison result signal as the first output signal when the clock enable signal has a second level.
12. The test system of claim 11, wherein the test unit of the memory region comprises memory cell arrays configured to commonly share a same bit line in a mat.
13. The test system of claim 11, wherein the semiconductor device is configured to compare the expectation data with the read data corresponding to next addresses after the first address when the reference data has a pass determination level.
15. The test system of claim 11, wherein the tester provides the semiconductor device with next addresses after the first address under a second test condition having a low probability for generating a temporary fail determination.
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April 2, 2020
January 24, 2023
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