The present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit and a driving method thereof, and a display device. The shift register unit includes: a first shift register, a second shift register and a switch control circuit, signal input terminals of the first and second shift registers are coupled to a cascade signal input terminal through the switch control circuit, the switch control circuit is configured to allow a current between the signal input terminal of the first shift register and the cascade signal input terminal or not, and allow a current between the signal input terminal of the second shift register and the cascade signal input terminal or not; the first shift register and the second shift register are configured such that at least one of them operates upon receiving a cascade signal provided by the cascade signal input terminal.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The shift register unit of claim 1, wherein the input sub-circuit comprises a first transistor, a control electrode of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the pull-up node.
3. The shift register unit of claim 1, wherein the pull-down control sub-circuit comprises a second transistor and a third transistor, a control electrode of the second transistor is coupled to the pull-up node, a first electrode of the second transistor is coupled to the pull-down node, and a second electrode of the second transistor is coupled to the first clock signal terminal; a control electrode of the third transistor is coupled to the first clock signal terminal, a first electrode of the third transistor is coupled to the first operating voltage terminal, and a second electrode of the third transistor is coupled to the pull-down node.
4. The shift register unit of claim 1, wherein the output sub-circuit comprises a fourth transistor and a fifth transistor, a control electrode of the fourth transistor is coupled to the pull-down node, a first electrode of the fourth transistor is coupled to the second operating voltage terminal, and a second electrode of the fourth transistor is coupled to the signal output terminal; and a control electrode of the fifth transistor is coupled to the pull-up node, a first electrode of the fifth transistor is coupled to the signal output terminal, and a second electrode of the fifth transistor is coupled to the second clock signal terminal.
5. The shift register unit of claim 4, wherein the output sub-circuit further comprises an eighth transistor, a first capacitor, and a second capacitor, wherein a control electrode of the eighth transistor is coupled to the first operating voltage terminal, a first electrode of the eighth transistor is coupled to the pull-up node, and a second electrode of the eighth transistor is coupled to the control electrode of the fifth transistor; a first terminal of the first capacitor is coupled to the control electrode of the fifth transistor, and a second terminal of the first capacitor is coupled to the signal output terminal; a first terminal of the second capacitor is coupled to the pull-down node, and a second terminal of the second capacitor is coupled to the first electrode of the fourth transistor.
6. The shift register unit of claim 1, wherein the pull-down sub-circuit comprises a sixth transistor and a seventh transistor, a control electrode of the sixth transistor is coupled to the pull-down node, a first electrode of the sixth transistor is coupled to the second operating voltage terminal, a second electrode of the sixth transistor is coupled to a first electrode of the seventh transistor, a control electrode of the seventh transistor is coupled to the second clock signal terminal, and a second electrode of the seventh transistor is coupled to the pull-up node.
15. A display device, comprising: the gate driving circuit of claim 14.
16. A display device, comprising: the gate driving circuit of claim 13.
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May 21, 2021
January 31, 2023
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