A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The semiconductor device according to claim 1, further comprising a first test circuit configured to output a first test pattern signal to the first row encoder and the second row encoder when in a test state.
4. The semiconductor device according to claim 1, further comprising a second test circuit configured to output a second test pattern signal to the first column encoder and the second column encoder when in a test state.
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January 26, 2021
January 31, 2023
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