The systems and methods described herein involve a device that may receive a plurality of commands and generate a common command indicative of matching data signals between each of the plurality of commands. The device may include a first latch that receives a shifted flag and outputs a shifted command in response to a first enable signal. The device may include shifters, where a first shifter may receive the common command, and a last shifter may couple to the first latch. The last shifter may receive a shifter common command and may generate the first enable signal using the shifted common command.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The device of claim 2, wherein the second latch is coupled to the third shifter, and wherein the second latch is configured to receive a decoded flag and to output the decoded flag in response to the second enable signal.
4. The device of claim 3, comprising a decoder configured to generate four decoded flags based at least in part on two command flags corresponding to the plurality of commands, wherein the four decoded flags comprise the decoded flag, and wherein values of each of the two command flags comprise values for each of the plurality of commands over time.
5. The device of claim 1, wherein the input stage comprises a sampling circuitry configured to identify the matching data signals between each of the plurality of commands based at least in part on identifying which address bits are shared by each of the plurality of commands.
6. The device of claim 5, wherein the sampling circuitry is configured to output the address bits as the common command.
7. The device of claim 6, wherein any remaining address bits of the plurality of commands are configured to be transmitted via a flag decoder configured to recapture the plurality of commands based on the remaining address bits in response to the common command being output from the second shifter.
8. The device of claim 1, wherein the input stage comprises an OR logic gate.
9. The device of claim 1, wherein a pair of address stages transmit a burst chop address during a partially overlapping time period with transmission of the common command.
10. The device of claim 1, wherein the plurality of commands comprises a read command, a read non-target command, a write command, a write non-target command, or any combination thereof.
12. The method of claim 11, comprising generating, via the command shifter, the second enable signal as the common command.
14. The method of claim 13, wherein the plurality of storage and processing stages are configured to transmit respective decoded flags including the decoded flag at different times corresponding to rising edges of the common command.
15. The method of claim 14, wherein the respective decoded flags each comprise a combination of logic signals indicative of memory command types comprising a read command type, a read non-target command type, a write command type, and a write non-target command type.
17. The system of claim 16, wherein the shifting circuitry is configured to compensate for a transmission delay during transmission of the plurality of memory commands through the command shifter via a walkback operation.
18. The system of claim 16, wherein the data signal common to each of the plurality of memory commands is generated in response to a logic gate toggling an output based on respective active levels of each of the plurality of memory commands.
20. The system of claim 16, wherein the memory bank control circuitry is configured to write or read data from a memory bank responsive to the plurality of shifted memory commands.
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October 14, 2021
February 7, 2023
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