A processor comprises a first register to store an encoded pointer to a memory location. First context information is stored in first bits of the encoded pointer and a slice of a linear address of the memory location is stored in second bits of the encoded pointer. The processor also includes circuitry to execute a memory access instruction to obtain a physical address of the memory location, access encrypted data at the memory location, derive a first tweak based at least in part on the encoded pointer, and generate a keystream based on the first tweak and a key. The circuitry is to further execute the memory access instruction to store state information associated with memory access instruction in a first buffer, and to decrypt the encrypted data based on the keystream. The keystream is to be generated at least partly in parallel with accessing the encrypted data.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The processor of claim 2, wherein the first buffer further includes the linear address of the memory location, a size of data requested by the memory access instruction, and the encrypted data.
10. The processor of claim 9, wherein the pipeline operations include using the speculative physical address to access the encrypted data at the memory location.
11. The processor of claim 6, wherein the slice of the linear address stored in the second bits of the encoded pointer includes the plaintext portion of the linear address.
12. The processor of claim 6, wherein the plaintext portion of the linear address is stored externally to the encoded pointer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 29, 2020
February 7, 2023
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