A memory structure, device, and method of making the same, the memory structure including a surrounding gate thin film transistor (TFT) and a memory cell stacked on the GAA transistor. The GAA transistor includes: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; and a gate electrode surrounding the high-k dielectric layer. The memory cell includes a first electrode that is electrically connected to the drain electrode.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The memory structure of claim 1, wherein the high-k dielectric layer and the channel are disposed within a through hole formed in the gate electrode.
3. The memory structure of claim 1, wherein the channel and the memory cell are column-shaped and are vertically stacked on a substrate, such that long axes of the channel and the memory cell are perpendicular to a plane of the substrate.
4. The memory structure of claim 3, wherein the gate electrode and the high-k dielectric layer laterally surround the channel in a direction parallel to the plane of the substrate.
5. The memory structure of claim 1, wherein the memory cell comprises a magneto-resistive random-access memory (MRAM) cell.
6. The memory structure of claim 1, wherein the memory cell comprises a magnetic tunnel junction (MTJ) disposed between the first and second electrodes.
7. The memory structure of claim 1, wherein the channel comprises indium gallium zinc oxide (IGZO).
9. The memory device of claim 8, wherein the surrounding gate TFT further comprises a surrounding gate insulator (SGI) disposed between the channel and the gate electrode.
10. The memory device of claim 9, wherein the channel is disposed in a through hole formed in the gate electrode.
12. The memory device of claim 8, further comprising dielectric spacers disposed between adjacent word lines.
13. The memory device of claim 8, further comprising a first dielectric layer disposed on the word lines and comprising a through hole in which the drain electrode is disposed.
14. The memory device of claim 13, further comprising a second dielectric layer disposed on the first dielectric layer and comprising a through hole in which the memory cell is disposed.
15. The memory device of claim 8, wherein the memory cell comprises a magneto-resistive random-access memory (MRAM) cell.
16. The memory device of claim 8, wherein the memory cell comprises a magnetic tunnel junction (MTJs) disposed between the first and second electrodes.
17. The memory device of claim 8, wherein the channel comprises indium gallium zinc oxide (IGZO).
19. The method of claim 18, wherein the semiconductor material comprises indium gallium zinc oxide (IGZO).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 12, 2021
February 14, 2023
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.