A trigger signal provided via a pulse-per-second input port of a network interface controller is detected. In response to the trigger signal, an internal hardware clock value of the network interface controller is recorded. The recorded internal hardware clock value is reported, wherein the reported internal hardware clock value is reported for use in determining a timing error of the network interface controller based at least in part on a comparison with a time value of another device that also received the trigger signal.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein detecting the trigger signal includes determining that a signal received at the pulse-per-second input port is the trigger signal and not another type of signal that is received at the pulse-per-second input port.
3. The method of claim 1, wherein the signal generator is able to generate waveforms with sharply rising and/or falling edges.
4. The method of claim 1, wherein the trigger signal is one of a plurality of trigger signals repeatedly provided via the pulse-per-second input port with a specified periodicity.
5. The method of claim 1, wherein the internal hardware clock value is represented as a plurality of binary digits.
6. The method of claim 1, wherein recording the internal hardware clock value includes transferring a digital representation of the internal hardware clock value from a physical hardware counter to a hardware register.
7. The method of claim 1, wherein reporting the recorded internal hardware clock value includes transmitting the recorded internal hardware clock value via a network to a programmed computer system.
8. The method of claim 7, wherein the network is a local area network.
9. The method of claim 7, wherein the programmed computer system includes a user input component, a display component, and a data storage component.
10. The method of claim 1, wherein the timing error is a difference value calculated as the reported internal hardware clock value subtracted from the time value of the second network interface controller or vice versa.
11. The method of claim 1, wherein the time value of the second network interface controller is designated as a more accurate time than the internal hardware clock value.
12. The method of claim 11, wherein the time value of the second network interface controller is derived from an atomic clock or a GPS time source.
13. The method of claim 1, wherein the trigger signal is received by the second network interface controller at the same or substantially same time as the trigger signal is received by the first network interface controller.
14. The method of claim 1, wherein the time value of the second network interface controller is recorded by the second network interface controller at the same or substantially same time as the internal hardware clock value of the first network interface controller is recorded.
15. The method of claim 1, wherein the second network interface controller includes its own pulse-per-second input port through which the trigger signal was received at the second network interface controller.
16. The method of claim 1, wherein the first network interface controller includes a pulse-per-second output port.
17. The method of claim 1, wherein the timing error of the first network interface controller is utilized in synchronizing clock values of the first network interface controller and the second network interface controller.
20. The system of claim 19, wherein the trigger signal is one of a plurality of trigger signals repeatedly provided via the first and second pulse-per-second input ports with a specified periodicity.
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May 21, 2020
February 14, 2023
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