A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The microelectronic device of claim 1, further comprising a back end of line (BEOL) structure on a side of a semiconductive base structure of the first die opposite the first control logic region.
3. The microelectronic device of claim 1, further comprising a back end of line (BEOL) structure on a side of a base semiconductive structure of the second die opposite the second control logic devices.
4. The microelectronic device of claim 1, wherein a horizontal area of the first die is substantially the same as a horizontal area of the second die.
5. The microelectronic device of claim 1, wherein the first control logic region of the first die is confined within horizontal boundaries of the memory array region of the first die.
6. The microelectronic device of claim 1, further comprising a third die coupled to the second die, the third die comprising a third control logic region comprising substantially the same types of control logic devices as the second control logic region.
7. The microelectronic device of claim 1, wherein the first control logic devices further comprise a voltage pump and a block switch.
8. The microelectronic device of claim 1, wherein the second control logic devices further comprise at least one I/O device, at least one sense amplifier, and a data path.
9. The microelectronic device of claim 1, wherein an operating voltage of the second control logic devices are lower than operating voltages of the first control logic devices.
11. The method of claim 10, wherein attaching the first die to the second die comprises positioning the memory array region between the first control logic region and the second control logic region.
12. The method of claim 10, further comprising forming the first control logic region to comprise at least one voltage pump and at least one block switch.
14. The method of claim 10, wherein forming a second die comprising a second control logic region including at least one page buffer comprises forming one page buffer for every bit line of the memory array region.
15. The method of claim 10, wherein forming a second die comprising a second control logic region comprises forming the second control logic region to comprise second control logic devices configured to operate at relatively lower voltages than first control logic devices of the first die.
16. The method of claim 10, further comprising, after attaching the first die to the second die, forming a back end of line (BEOL) structure vertically neighboring one of the first die or the second die.
17. The method of claim 10, further comprising, attaching a third die to the second die, the third die comprising at least one additional page buffer.
18. The method of claim 10, wherein forming a second die comprises forming the second die to have substantially the same horizontal area as the first die.
20. The microelectronic device of claim 19, further comprising a third control logic region underlying the second control logic region, the third control logic region comprising substantially the same control devices as the second control logic region.
21. The microelectronic device of claim 19, wherein the additional control logic devices located within the area defined by the memory array region comprise at least one voltage pump.
22. The microelectronic device of claim 19, wherein the second control logic region comprises one or more sense amplifiers, one or more I/O devices, and controller logic.
23. The microelectronic device of claim 19, wherein the additional control logic devices comprise at least one block switch and at least one voltage pump.
24. The microelectronic device of claim 19, wherein the second control logic region comprises CMOS circuitry configured to operate at applied voltages within a range of from about 0.7 V to about 1.4 V.
27. The method of claim 25, further comprising coupling bond pad structures of the second microelectronic device structure to bond pads of a third microelectronic device structure comprising at least an additional page buffer.
28. The method of claim 25, wherein forming a second microelectronic device structure comprises forming a second microelectronic device structure comprising a second control logic region comprising data path, at least one I/O device, and controller logic.
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July 17, 2020
February 21, 2023
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