Provided is a processor implemented method that includes performing training or an inference operation with a neural network by obtaining a parameter for the neural network in a floating-point format, applying a fractional length of a fixed-point format to the parameter in the floating-point format, performing an operation with an integer arithmetic logic unit (ALU) to determine whether to round off a fixed point based on a most significant bit among bit values to be discarded after a quantization process, and performing an operation of quantizing the parameter in the floating-point format to a parameter in the fixed-point format, based on a result of the operation with the ALU.
Legal claims defining the scope of protection, as filed with the USPTO.
10. A non-transitory computer-readable recording medium having recorded thereon a computer program, which, when executed by a computer, performs the method of claim 1.
18. The neural network apparatus of claim 15, wherein when the floating-point format is a single-precision floating-point format, the bias constant is a decimal number of 127, the number of bits of the first mantissa value is a decimal number of 23, and the predetermined number is a decimal number of 22, and when the floating-point format is a double-precision floating-point format, the bias constant is a decimal number of 1023, the number of bits of the first mantissa value is a decimal number of 52, and the predetermined number is a decimal number of 51.
20. The neural network apparatus of claim 11, further comprising a memory storing instruction, which when executed by the processors, configure the processor to perform the obtaining of the parameter, the applying of the fractional length to the floating-point format, the determining, and the quantizing of the parameter.
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October 15, 2018
February 28, 2023
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